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Calibre DFM Adds Bidirectional DEF Integration

Calibre DFM Adds Bidirectional DEF Integration
by Tom Simon on 01-26-2021 at 6:00 am

Siemens EDA DFM flow

GDS and LEF/DEF each came about to support data exchange in different types of design flows, custom layout and place & route respectively. GDS (or stream format) was first created in the late 1970s to support the first generation of custom IC layout tools, such as Calma’s GDSII system. Of course, the GDS format has been updated… Read More


Automotive SoCs Need Reset Domain Crossing Checks

Automotive SoCs Need Reset Domain Crossing Checks
by Tom Simon on 01-19-2021 at 6:00 am

reset domain crossing verification

When the number of clock domain crossings (CDCs) in SoCs proliferated it readily became apparent that traditional verification methods were not well suited to ensuring that they were properly handled in the design. This led to the creation of new methods and tools to check for correct interfaces between domains. Now, in automotive… Read More


Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation

Siemens EDA is Applying Machine Learning to Back-End Wafer Processing Simulation
by Mike Gianfagna on 01-18-2021 at 6:00 am

Siemens EDA is Applying Machine Learning to Back End Wafer Processing Simulation

There’s a lot to unpack in the title of this post. First, Siemens EDA is the new name for Mentor, a Siemens Business. The organization continues to operate as part of Siemens Digital Industries Software.  The organization has released a white paper that describes research done with the American University of Armenia. The work examines… Read More


CDC, Low Power Verification. Mentor and Cypress Perspective

CDC, Low Power Verification. Mentor and Cypress Perspective
by Bernard Murphy on 01-13-2021 at 6:00 am

CDC Low Power

Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More


Multicore System-on-Chip (SoC) – Now What?

Multicore System-on-Chip (SoC) – Now What?
by Daniel Nenni on 12-24-2020 at 6:00 am

Mentor Nucleus RTOS

A quick Q&A with Jeff Hancock, senior product manager for Mentor Embedded Platform Solutions, Siemens Digital Industries Software. Jeff oversees the Nucleus® real-time operating system (RTOS) and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services. Over the… Read More


Smoother MATLAB to HLS Flow

Smoother MATLAB to HLS Flow
by Bernard Murphy on 12-09-2020 at 6:00 am

A better design path from MATLAB 1 min

It hard to imagine design of a complex signal processing or computer vision application starting somewhere other than in MATLAB. Prove out the algorithm in MATLAB, then re-model in Simulink, to move closer to hardware. First probably an architectural model, using MATLAB library functions to prove out behavior of the larger system.… Read More


A Fast Checking Methodology for Power/Ground Shorts

A Fast Checking Methodology for Power/Ground Shorts
by Tom Dillinger on 12-01-2020 at 10:00 am

Figure 4

The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow.  The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Mentor User2User Virtual Event 2020!

Mentor User2User Virtual Event 2020!
by Daniel Nenni on 10-30-2020 at 6:00 am

banner u2u2020 virtual digital 500x350px 5

Now that we have gone virtual, life has never been easier, for me anyway. There are literally events every day beamed into my living room. The question is which should I attend? The answer is I should attend the ones with the most customer-based content, which is what User2User is all about. I will miss attending this one live as it was… Read More


ASIC and FPGA Design and Verification Trends 2020

ASIC and FPGA Design and Verification Trends 2020
by Daniel Nenni on 10-28-2020 at 6:00 am

2020 Wilson Report Verification ASIC FPGA

Harry Foster and I started in semiconductors at the same time so it was great to reminisce while talking about the latest Wilson Research Group Functional Verification Trend reports. Before I get into the reports lets talk about Harry who is a verification superstar:

Harry is Chief Scientist Verification for the Design Verification… Read More