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My recent post on a high-profile chip performance issue got me thinking. The root cause of the problem discussed there had to do with a clock tree circuit that was particularly vulnerable to reliability aging under elevated voltage and temperature. Chip aging effects have always got my attention. I’ve lived through a few of them… Read More
We‘re all aware of the challenges aging brings. I find the older I get, the more in touch I feel with those challenges. I still find it to be true that aging beats the alternative. I think most would agree. Human factors aside, I’d like to discuss the aging process as applied to the realm of semiconductor device physics. Here, as with… Read More
As voltages go down and frequencies increase, the challenges in chip design become increasingly complex and unforgiving. Issues that once seemed manageable now escalate, while new obstacles emerge, demanding our attention. Among these challenges, clock jitter stands out as a formidable threat. At its core, clock jitter is… Read More
Digital logic chips synchronize all logic operations by using a clock signal connected to flip-flops or latches, and the clock is distributed across the entire chip. The ultimate goal is to have a clock signal that arrives at the exact same moment in time at all clocked elements. If the clock arrives too early or too late from the PLL… Read More
In the realm of digital systems, clocks play a crucial role in synchronizing various components and ensuring smooth flow of logic propagation. However, the accuracy of clocks can be significantly affected by power supply induced jitter. Jitter refers to the deviation in the timing of clock signals with PDN noise compared to ideal… Read More
The relentless advancement of mobile phone technology continues to push boundaries, demanding SoCs that deliver ever-increasing performance while preserving extensive battery life. To meet these demands, the industry is progressively embracing lower technology nodes with current designs being taped-out at 5nm or below.… Read More
Zakir Hussain is a co-founder of Infinisim and brings over 25 years of experience in the Electronic Design Automation industry. He was at Simplex Solutions, Inc. (acquired by Cadence) at its inception in 1995 through the end of 2000. He has published numerous papers on verification and simulation and has presented at many industry… Read More
Semiconductor chips are all tested prior to shipment in order to weed out early failures, however there are some more subtle reliability effects that only appear in the longer term, like clock aging. There’s even a classic chart that shows the “bathtub curve” of failure rates over time:
If reality and expectations… Read More
In the good old days the clock signal looked like a square wave , and had a voltage swing of 5 volts, however with 7nm technology the clock signals can now look more like a sawtooth signal and may not actually reach the full Vdd value of 0.65V inside the core of a chip. I’ll cover some of the semiconductor market trends, and then challenges… Read More
Synchronous circuits dominate the electronic world because clocking eases the design of circuits compared to asynchronous circuits. At the same time, clocking also introduces its share of challenges to overcome. No wonder, a tremendous amount of time and effort have been spent over the years on developing and implementing … Read More
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