Agnisys Inc. a leader in design and verification automation for hardware development, is gearing up for an impactful presence at DAC 2024. This year’s participation will be marked by various activities designed to engage and inspire the electronic design automation (EDA) community. Attendees can look forward to our … Read More
2024 Outlook with Anupam Bakshi of Agnisys
We have worked with Agnisys for the last two years and it has been a pleasure. Anupam and his team of specification automation experts have pioneered a family of products and solutions for streamlining the generation of the required files for design, software, verification, validation, and documentation for semiconductor development… Read More
WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
This webinar looks at the challenges a Design Engineer could face, such as when various IP blocks within an SoC are required to work in different clock domains to satisfy the power constraints.
Abstract:
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints.… Read More
An Update on IP-XACT standard 2022
Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges. Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More
WEBINAR: Driving Golden Specification-Based IP/SoC Development
The ever-increasing demands placed on Intellectual Property (IP) and System-on-Chip (SoC) development teams have resulted in an ever-increasing need for automation solutions that can boost productivity without contributing to further risk. Certainly, demands for automation have long been the drivers behind the growth… Read More
The Inconvenient Truth of Clock Domain Crossings
Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More
Visit with Agnisys at DAC 2023 in San Francisco July 10-12
I’d like to extend an invitation to you and your development team to visit with Agnisys in our booth, #2512, at this week’s Design Automation Conference (DAC) 2023, Monday, July 10-12.
In its 60th year, DAC is recognized as the premier event for the design and design automation of electronic chips to systems, so you can count on team… Read More
Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?
Whether it is fully autonomous driving, or wrinkle-free fabric, or ambient energy harvesting for powering electronic devices, each industry is chasing after its respective ultimate goal. For the semiconductor design industry, its goal is the capability to generate complete chip or IP in executable format from a high-level… Read More
ISO 26262: Feeling Safe in Your Self-Driving Car
The word “safety” can mean a lot of different things to different people, but it’s a word we hear frequently when the topic involves automobiles. In contrast, “functional safety” has a long-established meaning in the design of electrical and mechanical systems: an automatic protection mechanism with a predictable response … Read More
DAC 2021 – What’s Up with Agnisys and Spec-driven IC Development
Walking the exhibit floors at DAC in December I spotted the familiar face of Anupam Bakshi, Founder and CEO of Agnisys, so I stopped by the booth to get an update on his EDA company. My first question for him was about the origin of the company name, Agnisys, and I found at that Agni means Fire in Sanskrit, one of the five elements.
The … Read More