The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as Frontier… Read More
Artificial Intelligence
Must-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More
The Other Side of Bug Localization
Automated debugging – starting from an unexpected behavior to find a bug root-cause or a small set of possible root-causes – is a hot topic now that agentic systems are playing a bigger role in automation. Unsurprising since debug remains the most time and resource-consuming aspect of verification, in turn the most time/resource-consuming… Read More
Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026
Si2 is conducting quite a few sessions at DAC this year covering everything from power model standards to agentic AI. There is one session that is a bit different, focusing on LLM benchmarking. Since AI is popping up everywhere, the ability to accurately assess and measure the quality of new models becomes more important. That’s… Read More
RISC-V Advantage in Accelerator Control Highlights System Verification Challenges
When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled to understand the appeal in head-on competition with Arm in premium applications such as servers and infrastructure systems.… Read More
The Architecture of Success: Why a Unified Semiconductor IP Strategy Is the Foundation of Modern SoC Design
As architects push toward advanced nodes and increasingly demanding workloads, modern silicon design has entered an era of unprecedented complexity. A single design respin can cost millions of dollars and delay market entry. Against this backdrop, designs must be balanced for performance, bandwidth, power efficiency, security… Read More
CEO Interview with Madhulima Tewari of VerifAIX
Madhulima Tewari is the CEO and founder of VerifAIX. After two decades building EDA tools, taping out chips, and working on distributed systems, cloud infrastructure, and enterprise AI applications, she teamed up with chip design and methodology leaders and university researchers to build an agentic AI system aimed at helping… Read More
TSMC’s Raises the Bar on CAPEX!
On the latest investor call the big story was the increase in CAPEX for 2026 and the expected CAPEX for 2027. TSMC raised the CAPEX ceiling for 2026 from US$56 billion to US$64 billion. My guess would be US$64 billion will be spent if not more. We have been discussing this in the SemiWiki Forum and my guess for the 2027 TSMC CAPEX is an incredible… Read More
PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity
PCI Express (PCIe), PCIe switches, Time Division Multiplexing (TDM), Network Interface Cards (NICs), and SmartNICs are all well-established technologies that have formed the backbone of computing and networking systems for years. More recently, SuperNICs have emerged as the next generation of networking devices optimized… Read More
Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.
This transition is clearly validated by TSMC’s 2025 filings, which show… Read More


Intel and TSMC Take Different Paths to High-NA EUV