Banner Electrical Verification The invisible bottleneck in IC design updated 1
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Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation

Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation
by Daniel Nenni on 11-03-2025 at 6:00 am

Synopsys Nvidia Agentic AI 2025

In a landmark announcement at NVIDIA’s GTC Washington, D.C. conference Synopsys unveiled deepened collaborations with NVIDIA to revolutionize semiconductor design and engineering through agentic AI, GPU-accelerated computing, and AI-driven physics simulations. This partnership, building on over three decades… Read More


Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business

Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business
by Daniel Nenni on 10-31-2025 at 6:00 am

Lip Bu Tan Intel

The second chapter of our book “Fabless: The Transformation of Semiconductor Industry” describes the ASIC business and how important it is. That was more than 10 years ago and the ASIC business is still at the forefront of the Semiconductor industry and is a key enabler of the AI revolution we are experiencing today.

First let’s … Read More


Quadric: Revolutionizing Edge AI

Quadric: Revolutionizing Edge AI
by Daniel Nenni on 10-30-2025 at 10:00 am

Revolutionizing Edge AI SemiWiki Blog Image

In the rapidly evolving landscape of AI, Quadric stands out as a pioneering force in edge computing. Founded in 2018 and headquartered in Burlingame, California, Quadric is a technology company focused on developing high-performance, energy-efficient processors for AI workloads at the edge devices like smartphones, IoT … Read More


Inference Acceleration from the Ground Up

Inference Acceleration from the Ground Up
by Lauro Rizzatti on 10-29-2025 at 6:00 am

VSORA AI CHip

VSORA, a pioneering high-tech company, has engineered a novel architecture designed specifically to meet the stringent demands of AI inference—both in datacenters and at the edge. With near-theoretical performance in latency, throughput, and energy efficiency, VSORA’s architecture breaks away from legacy designs optimized… Read More


Emulator-Like Simulation Acceleration on GPUs. Innovation in Verification

Emulator-Like Simulation Acceleration on GPUs. Innovation in Verification
by Bernard Murphy on 10-28-2025 at 6:00 am

Innovation New

GPUs have been proposed before to accelerate logic simulation but haven’t quite met the need yet. This is a new attempt based on emulating emulator flows. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series… Read More


CEO Interview with Wilfred Gomes of Mueon Corporation

CEO Interview with Wilfred Gomes of Mueon Corporation
by Daniel Nenni on 10-27-2025 at 2:00 pm

wilfred gomes

Wilfred Gomes is the co-founder, CEO, and president of Mueon Corporation, a next-generation infrastructure startup rethinking how data centers are built for the AI era. The company’s flagship innovation, Cubelets™, modular, stackable units that unite compute, memory, power delivery and thermal management, replace the … Read More


Pioneering Edge AI: TekStart’s Cognitum Processor Ushers in a New Era of Efficient Intelligence

Pioneering Edge AI: TekStart’s Cognitum Processor Ushers in a New Era of Efficient Intelligence
by Daniel Nenni on 10-27-2025 at 10:00 am

2510.1 Semiwiki Image 1

One of the more in interesting companies I met at the AI Infra Summit was a company known to me for some time. The most interesting part was the chip they are in the process of taping out; It is a high-performance, ultra-low-power AI processor purpose-built for edge computing. It is claimed to deliver “the processing muscle … Read More


Chiplets: Powering the Next Generation of AI Systems

Chiplets: Powering the Next Generation of AI Systems
by Kalar Rajendiran on 10-23-2025 at 10:00 am

Arm Synopsys at Chiplet Summit

AI’s rapid expansion is reshaping semiconductor design. The compute and I/O needs of modern AI workloads have outgrown what traditional SoC scaling can deliver. As monolithic dies approach reticle limits, yields drop and costs rise, while analog and I/O circuits gain little from moving to advanced process nodes. To sustain … Read More


Better Automatic Generation of Documentation from RTL Code

Better Automatic Generation of Documentation from RTL Code
by Tom Anderson on 10-23-2025 at 6:00 am

Specador Doc

One technical topic I always find intriguing is the availability of links between documentation and chip design. It used to be simple: there weren’t any. Architects wrote a specification (spec) in text, in Word if they had PCs, or using “troff” or a similar format if they were limited to Unix platforms. Then the hardware designers… Read More


Learning from In-House Datasets

Learning from In-House Datasets
by Bernard Murphy on 10-22-2025 at 6:00 am

Training in a Constrained Environment min

At a DAC Accellera panel this year there was some discussion on cross-company collaboration in training. The theory is that more collaboration would mean a larger training set and therefore higher accuracy in GenAI (for example in RTL generation). But semiconductor companies are very protective of their data and reports of copyrighted… Read More