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Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration
by Kalar Rajendiran on 04-29-2026 at 10:00 am

CoWoS Enables AI Compute Scaling

The rapid rise of artificial intelligence is fundamentally reshaping computing architectures. As AI models scale toward trillions of parameters, traditional approaches to performance improvement are no longer sufficient. Instead, the industry is entering a new era where system-level innovation, advanced packaging, … Read More


The Shift to System-Level AI Drives Next-Generation Silicon

The Shift to System-Level AI Drives Next-Generation Silicon
by Kalar Rajendiran on 04-27-2026 at 8:00 am

TSMC Advanced Technology Roadmap

At its 2026 Technology Symposium, TSMC delivered a clear message: the AI era has entered a new phase. The primary constraint is no longer model capability, but the systems required to run those models at scale. Addressing this shift will demand significant advances in semiconductor technology, spanning compute, memory, interconnects,… Read More


proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets

proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets
by Mike Gianfagna on 04-21-2026 at 6:00 am

proteanTecs at Chiplet Summit – Changing the Game for Health & Performance Monitoring of Chiplets

The recent Chiplet Summit 2026 was a great place to learn about new chiplet designs, emerging standards, and a growing array of support technologies to help design and manufacture chiplet-based systems. In my travels at the show, I found a lot of technology that fit these descriptions. But there were also companies at the show that… Read More


CEO Interview with Dr. Hardik Kabaria of Vinci

CEO Interview with Dr. Hardik Kabaria of Vinci
by Daniel Nenni on 04-12-2026 at 12:00 pm

HardikKabariaHeadshot (1)

Hardik Kabaria is the founder and CEO of Vinci, a frontier lab building systems that make physical reality continuously computable.

While software has become programmable, physics has remained episodic—accessed through discrete simulations and approximations. Vinci is changing that. Under Kabaria’s leadership, the company

Read More

Podcast EP338: How Thermo Fisher Scientific Helps Advanced Semiconductor Development with Dr. Mohan Iyer

Podcast EP338: How Thermo Fisher Scientific Helps Advanced Semiconductor Development with Dr. Mohan Iyer
by Daniel Nenni on 04-03-2026 at 10:00 am

Daniel is joined by Dr. Mohan Iyer, who serves as the vice president and general manager of the Semiconductor Business Unit at Thermo Fisher Scientific, a global leader in providing reference metrology, defect characterization, and localization equipment. These advanced systems are essential for driving innovation, accelerating… Read More


Alchip’s Leadership in ASIC Innovation: Advancing Toward 2nm Semiconductor Technology

Alchip’s Leadership in ASIC Innovation: Advancing Toward 2nm Semiconductor Technology
by Daniel Nenni on 04-01-2026 at 10:00 am

Alchip’s Leadership in ASIC Innovation

Alchip Technologies has recently reported significant progress in the development of advanced 2nm  ASICs, positioning itself as a leader in next-generation semiconductor design for AI and HPC. The announcement highlights Alchip’s efforts to commercialize cutting-edge chip technologies and deliver highly customized … Read More


Synopsys Advances Hardware Assisted Verification for the AI Era

Synopsys Advances Hardware Assisted Verification for the AI Era
by Kalar Rajendiran on 03-26-2026 at 6:00 am

Software Defined HAV, Scalability, Density, Performance and EP Ready Hardware

At the 2026 Synopsys Converge Event, Synopsys announced a broad set of new products and platform upgrades, with its hardware-assisted verification (HAV) announcement emerging as a key highlight within that lineup. A key aspect of this announcement was moving beyond a hardware centric model to a more scalable, programmable … Read More


Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
by Kalar Rajendiran on 03-23-2026 at 10:00 am

Bump maps for HBM PHY and HBM memory

This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the InterconnectRead More


Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit

Arteris Highlights a Path to Scalable Multi-Die Systems at the Chiplet Summit
by Mike Gianfagna on 03-23-2026 at 6:00 am

Arteris Highlights a Path to Scalable Multi Die Systems at the Chiplet Summit

At the recent Chiplet Summit, presentations, discussions and general participation could be broken down into a few broad categories. There were presentations of actual chiplet designs, either as building blocks or end products. There were presentations regarding design tools and methodologies to support and accelerate … Read More


Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement
by Mike Gianfagna on 03-19-2026 at 8:00 am

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Enablement

The recent Chiplet Summit in Santa Clara was buzzing with new designs and new design methods. It felt like the industry had turned a corner at this year’s event with lots of new technology and design success on display. Siemens EDA had a large presence at the show and took home the Best in Show Award for Packaging Design. There were a … Read More