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Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
by Bernard Murphy on 10-21-2026 at 6:00 am

MultiDie FlexGen

Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and … Read More


The Industry Challenge: AI Is Forcing Semiconductor Innovation Beyond the Chip

The Industry Challenge: AI Is Forcing Semiconductor Innovation Beyond the Chip
by Kalar Rajendiran on 10-20-2026 at 10:00 am

Partners Photo Op scaled

Applied Materials President and CEO Gary Dickerson with the EPIC Center founding partners on October 12, 2026, in Sunnyvale, CA. (Tomas Ovalle/AP Content Services for Applied Materials, Inc.)The bottlenecks are becoming interconnected

Artificial intelligence is changing what the semiconductor industry must deliver. … Read More


CEO Interview with Dr. Raj Talluri of Kulicke & Soffa

CEO Interview with Dr. Raj Talluri of Kulicke & Soffa
by Daniel Nenni on 10-18-2026 at 6:00 am

Connecting the Future of Chips

Dr. Talluri joined K&S in August 2026 as a member of the Board and assumed the role of President and Chief Executive Officer of K&S in September 2026. Prior to joining K&S, Dr. Talluri served as President, Chief Executive Officer and a member of the Board of Directors at Enovix Corporation, a Nasdaq-listed advanced … Read More


Data Center Energy Trends Force a Rethink of Chip Power Delivery

Data Center Energy Trends Force a Rethink of Chip Power Delivery
by Daniel Nenni on 10-08-2026 at 10:00 am

Data Center Energy Trends Force a Rethink of Chip Power Delivery

Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary:

Artificial intelligence is changing the requirements for semiconductor innovation. Faster transistors and denser packaging remain essential, but their benefits increasingly depend on another engineering… Read More


Beyond the Die: Verifying the Connected Chip

Beyond the Die: Verifying the Connected Chip
by Daniel Nenni on 10-06-2026 at 10:00 am

Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems

One of the standout presentations at the 2026 TSMC OIP Forum highlighted a collaboration between Siemens EDA, Marvell, and TSMC. I always appreciate EDA presentations that bring together customer and foundry perspectives, and this one did not disappoint. We follow 3D IC technology closely and have published more than 150 blogs… Read More


TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies

TSMC OIP Ecosystem Forum 2026: Spotlight on Emerging Technologies
by Mike Gianfagna on 10-02-2026 at 8:00 am

TSMC OIP 2026 Emerging Technologies Alley

The TSMC OIP Ecosystem Forum highlighted many accomplishments across TSMC’s vast ecosystem. Specific achievements with TSMC as well as collaborative work across several companies were all on display.

And there was an exhibit area where you could meet the companies behind many of these stories and learn more about them.

This … Read More


TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems

TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
by Mike Gianfagna on 09-30-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Broadcom’s View of ASICs and Ecosystems

I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More


Why Advanced Chip Packaging Is Becoming a Design Problem

Why Advanced Chip Packaging Is Becoming a Design Problem
by Daniel Nenni on 09-29-2026 at 2:00 pm

Why Advanced Chip Packaging Is Becoming a Design Problem

As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More


Managing Power, Performance and Reliability in the Chiplet Era

Managing Power, Performance and Reliability in the Chiplet Era
by Kalar Rajendiran on 09-29-2026 at 10:00 am

Test Drivers proteanTecs (Chiplet Webinar)

Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More


TSMC OIP Ecosystem Forum 2026: Opening Remarks

TSMC OIP Ecosystem Forum 2026: Opening Remarks
by Mike Gianfagna on 09-28-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Opening Remarks

The 2026 TSMC Open Innovation Platform (OIP) Ecosystem Forum was held on September 23, 2026, in Santa Clara, CA. This is the event where TSMC showcases the substantial progress made with its massive semiconductor ecosystem. As one would expect, AI was a key topic throughout the day, with some very impressive results reported and… Read More