AI Models on Edge GPUs
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CPO’s Next Challenge: Turning Optical Performance into Manufacturable Systems

CPO’s Next Challenge: Turning Optical Performance into Manufacturable Systems
by Moh Kolb on 11-10-2026 at 10:00 am

CPO Challanges SemiWikI nov5

Why integration boundaries, assembly strategies, and manufacturing yield must be engineered together

The Shift from Optical Performance to Manufacturing Scale

Co-packaged optics (CPO) is moving beyond laboratory demonstrations toward commercial deployment in AI infrastructure. As switch bandwidth continues to increase,… Read More


Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs

Three-Dimensional Chess Anyone? The Challenges of Power Integrity for Multi-Die Designs
by Mike Gianfagna on 11-10-2026 at 6:00 am

Three Dimensional Chess Anyone? The Challenges of Power Integrity for Multi Die Designs

Power integrity has been a substantial design challenge for a long time. In the multi-die era, the problems associated with EMIR analysis must now move beyond the chip to consider interactions across the entire stack. The effects to be analyzed span a multi-dimensional, multi-material space. The graphic at the top of this post… Read More


Glass Is Becoming an AI Infrastructure Platform

Glass Is Becoming an AI Infrastructure Platform
by Moh Kolb on 11-05-2026 at 10:00 am

Glass substrate as arch SemiWiki oct5 (1) (1)

The value of glass will be determined not by its material properties alone, but by whether it can expand the package architecture window and be realized repeatedly at manufacturing scale.

AI infrastructure is pushing advanced packaging into a regime where the substrate itself increasingly determines what can be built.

As packages… Read More


The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
by Kalar Rajendiran on 11-05-2026 at 6:00 am

The Real Value of Predictable Execution

The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More


Reimagining 3D IC Design: From Architecture to Signoff

Reimagining 3D IC Design: From Architecture to Signoff
by Admin on 11-04-2026 at 8:00 am

figure1 digital twin creation

By Keith Felton, Andras Vass-Varnai and Todd Burkholder, Siemens EDA

The semiconductor industry is undergoing a fundamental transformation. Heterogeneous integration, the practice of combining multiple chiplets and specialized components into a single advanced packaging platform, has emerged as a powerful alternative… Read More


Agentic AI accelerates 3D IC engineering for the AI factory era

Agentic AI accelerates 3D IC engineering for the AI factory era
by Admin on 11-02-2026 at 6:00 am

Agentic AI Reimagines 3D IC Engineering

By Sudarshan Deo, software R&D Manager for 3D IC, Siemens

What if you could completely rethink what an EDA workflow looks like for the increasingly complex 3D ICs powering the next generation of AI factories? Siemens’ expanded agentic AI portfolio is automating the hardest parts of 3D IC engineering.

At NVIDIA GTC Berlin 2026,… Read More


Intel’s Tiny Bridges Could Lead to Very Big Paychecks

Intel’s Tiny Bridges Could Lead to Very Big Paychecks
by Daniel Nenni on 11-01-2026 at 12:00 pm

Tiny Chip Builders, Big Payday

Intel’s next big opportunity could come from something that sounds spectacularly unglamorous: connecting tiny pieces of silicon. Advanced packaging rarely attracts the attention lavished on powerful processors or artificial intelligence models. Yet it increasingly determines how effectively those technologies perform.… Read More


Inside the Package Powering Modern AI

Inside the Package Powering Modern AI
by Daniel Nenni on 10-26-2026 at 8:00 am

TSMC CoWoS is Critical to AI Chips

TSMC’s CoWoS-S is critical to the artificial intelligence era because it solves the central systems problem facing modern accelerators: computing capability is growing faster than conventional packages can supply data, power, and connectivity. CoWoS-S, meaning Chip-on-Wafer-on-Substrate with a silicon interposer, … Read More


From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation

From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation
by Kalar Rajendiran on 10-22-2026 at 10:00 am

Gary Dickerson on the Stage

The semiconductor industry has long depended on collaboration between technology developers, equipment suppliers and manufacturers. But as artificial intelligence reshapes computing, established ways of working together may no longer be sufficient. The next wave of innovation will depend not just on what companies develop,… Read More


Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
by Bernard Murphy on 10-21-2026 at 6:00 am

MultiDie FlexGen

Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and … Read More