CAST Compression IP Webinar 800x100 (2)
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Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling

Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling
by Kalar Rajendiran on 07-10-2025 at 10:00 am

What is SimLab

The semiconductor industry is rapidly moving beyond traditional 2D packaging, embracing technologies such as 3D integrated circuits (3D ICs) and 2.5D advanced packaging. These approaches combine heterogeneous chiplets, silicon interposers, and complex multi-layer routing to achieve higher performance and integration.… Read More


Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis

Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis
by Kalar Rajendiran on 07-01-2025 at 10:00 am

Innovator3D IC Solution Suite

In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More


Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA

Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA
by Daniel Nenni on 06-20-2025 at 8:00 am

Dan is joined by Dr. John Ferguson, Director of Product Management for the Calibre nmDRC and 3DIC related products for Siemens EDA. John has worked extensively in the area of physical design verification. Holding several patents, he is also a frequent author in the physical design and verification domain. Current activities … Read More


Arteris Expands Their Multi-Die Support

Arteris Expands Their Multi-Die Support
by Bernard Murphy on 06-18-2025 at 6:00 am

multi die use cases min

I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and… Read More


Altair at the 2025 Design Automation Conference #62DAC

Altair at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-17-2025 at 8:00 am

62nd DAC SemiWiki

Design Perfection from Concept to Tape-out Booth #1617 at DAC25 – June 23-25, 2025

Join us to learn how Altair’s world-class solutions are powering perfect semiconductor design.

The semiconductor industry operates at an accelerated pace, in which every second saved is a competitive advantage. You must rely on solutions

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Siemens EDA Outlines Strategic Direction for an AI-Powered, Software-Defined, Silicon-Enabled Future

Siemens EDA Outlines Strategic Direction for an AI-Powered, Software-Defined, Silicon-Enabled Future
by Kalar Rajendiran on 06-09-2025 at 6:00 am

Software defined Systems of Systems

In a keynote delivered at this year’s Siemens EDA User2User event, CEO Mike Ellow presented a focused vision for the evolving role of electronic design automation (EDA) within the broader context of global technology shifts. The session covered Siemens EDA’s current trajectory, market strategy, and the changing landscape … Read More


Synopsys Addresses the Test Barrier for Heterogeneous Integration

Synopsys Addresses the Test Barrier for Heterogeneous Integration
by Mike Gianfagna on 05-29-2025 at 10:00 am

Synopsys Addresses the Test Barrier for Heterogeneous Integration

The trend is clear, AI and HPC is moving to chiplet-based, or heterogenous design to achieve the highest levels of performance, while traditional monolithic system-on-chip (SoC) designs struggle to scale. What is also clear is the road to this new design style is not a smooth one. There are many challenges to overcome. Some are … Read More


Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies

Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies
by Kalar Rajendiran on 05-28-2025 at 10:00 am

Sassine Holding an 18A Test chip

Design-Technology Co-Optimization (DTCO) has been a foundational concept in semiconductor engineering for years. So, when Synopsys referenced DTCO in their April 2025 press release about enabling Angstrom-scale chip designs on Intel’s 18A and 18A-P process technologies, it may have sounded familiar—almost expected. … Read More


Alchip’s Technology and Global Talent Strategy Deliver Record Growth

Alchip’s Technology and Global Talent Strategy Deliver Record Growth
by Kalar Rajendiran on 05-20-2025 at 10:00 am

Alchip TSMC 2nm N2

Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building… Read More


Intel’s Foundry Transformation: Technology, Culture, and Collaboration

Intel’s Foundry Transformation: Technology, Culture, and Collaboration
by Kalar Rajendiran on 05-07-2025 at 10:00 am

Intel and UMC 2025

Intel’s historical dominance in semiconductor process technology began to erode around 2018, as competitors started delivering higher performance at smaller nodes. In response, Intel is now doubling down on innovation across two fronts: advanced process nodes such as Intel 18A and 14A, and cutting-edge packaging technologies.… Read More