For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test … Read More
Author: Mike Gianfagna
How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
How MZ Technologies is Making Multi-Die Design a Reality
The next design revolution is clearly upon us. Traditional Moore’s Law is slowing, but the exponential demand for innovation and form factor density is not. When you can no longer get it done with a single monolithic chip, moving to a multi-die approach is the answer. This emerging design methodology has many challenges – supply… Read More
Photonic Computing – Now or Science Fiction?
Cadence recently held an event to dig into the emerging world of photonic computing. Called The Rise of Photonic Computing, it was a two-day event held in San Jose on February 7th and 8th. The first day of the event was also accessible virtually. I attended a panel discussion on the topic – more to come on that. The day delivered a rich… Read More
Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
The relentless demand for lower power SoCs is evident across many markets. Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost… Read More
Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems
Multi-die system design is clearly gaining momentum. Part of this momentum focuses on chiplets and a chiplet ecosystem. A “building block” approach for design will work better if there is a way to get verified, quality building blocks in the form of chiplets. The recent Chiplet Summit became an epicenter for this topic. The conference… Read More
proteanTecs Addresses Growing Power Consumption Challenge with New Power Reduction Solution
proteanTecs is a unique company, delivering electronics visibility from within. Its core mission is to enable the electronics industry to continue to scale. The company achieves this goal by first embedding on-chip monitors, called Agents, during the design process to generate deep data on the chip’s profiling, health, and… Read More
A Rare Offer from The SHD Group – A Complimentary Look at the RISC-V Market
The web is a wonderful place to find information on almost any topic. While top-level information is easy to find, a deep dive often requires the services of a market research firm. These organizations specialize in “going deep” on many technology topics, offering insights not available with a Google search. And these services… Read More
How Codasip Unleashed CHERI and Created a Paradigm Shift for Secured Innovation
At the recent RISC-V Summit, Dr. Ron Black, CEO of Codasip unveiled a significant new capability to create a more secure environment for innovation. Rather than re-writing trillions of lines of code to solve the security problem, Ron described a much more practical approach. One that brought a research topic into mainstream deployment.… Read More
Analog Bits Enables the Migration to 3nm and Beyond
The world is abuzz with 3nm and 2nm technology availability. These processes offer the opportunity to pack far more on a single die than ever before. The complex digital systems contemplated will bring new AI algorithms to life and much more. But there is another side of the technology migration story. With all that digital processing… Read More
Achieving a Unified Electrical/Mechanical PCB Design Flow – The Siemens Digital Industries Software View
Let’s face it, designs are getting harder, much harder. Gone are the days when the electrical and mechanical design of a system occurred separately. Maybe ten years ago this practice was acceptable. Once the electrical design was completed (either the chip or the board) the parameters associated with the design were then given… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay