At the recent RISC-V Now by Andes conference, Aion Silicon’s presentation made one thing clear: RISC-V is no longer an emerging alternative but rather rapidly becoming foundational to modern silicon design. This conviction is not theoretical says Oliver Jones, CEO of Aion Silicon, who gave the talk. It is grounded in Aion Silicon’s… Read More
Author: Kalar Rajendiran
RISC-V: From Niche Architecture to Strategic Foundation
Synopsys and TSMC Deepen AI Design Alliance: What It Means
A recent announcement from Synopsys signals a meaningful escalation in the race to build next-generation AI hardware. The expanded collaboration between Synopsys and TSMC brings together silicon-proven IP, AI-driven design tools, and cutting-edge manufacturing processes in a tightly integrated effort to accelerate high-performance… Read More
Connecting the Dots: Why RISC-V System Design Is Entering a New Era
At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real focus has moved up the stack to system-level design. This is where connectivity, integration, and security define whether an innovation… Read More
Rethinking ECAD IT Infrastructure: From Fragmentation to an Engineering Platform
The semiconductor industry is entering a new phase of complexity. Advanced nodes, heterogeneous integration, and AI-driven design workflows are placing unprecedented demands on engineering teams. While much of the focus remains on tools and methodologies, an equally critical constraint is emerging beneath the surface:… Read More
Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration
The rapid rise of artificial intelligence is fundamentally reshaping computing architectures. As AI models scale toward trillions of parameters, traditional approaches to performance improvement are no longer sufficient. Instead, the industry is entering a new era where system-level innovation, advanced packaging, … Read More
The Shift to System-Level AI Drives Next-Generation Silicon
At its 2026 Technology Symposium, TSMC delivered a clear message: the AI era has entered a new phase. The primary constraint is no longer model capability, but the systems required to run those models at scale. Addressing this shift will demand significant advances in semiconductor technology, spanning compute, memory, interconnects,… Read More
Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions
Semiconductor manufacturing has become one of the most data-intensive industrial environments in the world, and AI is rapidly becoming central to how fabs operate and optimize. Yet, rather than converging on a single model for AI adoption, the industry is evolving along two distinct paths. One centered on platform-scale… Read More
RISC-V Has Momentum. The Real Question Is Who Can Deliver
RISC-V has momentum. The industry knows it. The harder question is: who can actually deliver when and where it matters?
A Shift That Changes the Stakes
On March 24, 2026, Arm made something explicit: it is now a silicon company. After decades as a neutral IP provider, Arm is moving up the stack. It’s building chips and complete solutions,… Read More
Synopsys Advances Hardware Assisted Verification for the AI Era
At the 2026 Synopsys Converge Event, Synopsys announced a broad set of new products and platform upgrades, with its hardware-assisted verification (HAV) announcement emerging as a key highlight within that lineup. A key aspect of this announcement was moving beyond a hardware centric model to a more scalable, programmable … Read More
Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces
This article concludes the three-part series examining key methodologies required for successful multi-die design. The first article Reducing Risk Early: Multi-Die Design Feasibility Exploration focused on feasibility exploration and early architectural validation, while the second article Building the Interconnect… Read More
Solving the EDA tool fragmentation crisis