I first heard about SPICE Vision Pro when working at Mentor Graphics where we needed a way to visualize SPICE netlists and debug SPICE simulation results node by node on a design where we didn’t have the original schematics. Last Monday I met the engineers from Concept Engineering in their booth at DAC to get an update, Gerhard… Read More
Author: Daniel Payne
Fast SPICE from Kiev at DAC
Monday at DAC I met with an EDA start-up called Symica based in Kiev. Ian Tsybulkin, CEO met with me to give an overview of their tools.… Read More
A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
Linda Fosler, Tom Daspit and Mitch from Mentor Graphics met with me last Monday at DAC to provide an update on IC layout and circuit simulation tools. My notes follow:
Overview – Pyxis for Schematic and Layout, IC Station is re-branded as Pyxis. (Pyxis schematic is still Falcon, Ample language is still used.)… Read More
ST using Cadence IC Tools with Module Generators
Cadence invited Francois Lemery of ST Microelectronics to speak at a luncheon last Monday at DAC about designing for the 20nm node using module generators. Here are my trip report notes:
Schematic, IC Layout, Clock and Timing Closure from ICScape
Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.
Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)
ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun… Read More
Fast Monte Carlo and Analog Fast SPICE
Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.
In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach… Read More
Collaboration at 28nm, 20nm and 14nm
Wednesday morning I attended a panel discussion with: ARM, IBM, Cadence, GLOBALFOUNDRIES and Samsung.
The panelists all sang the same song of collaboration between EDA, IP and Foundry to enable 28nm, 20nm and even 14nm.… Read More
Physical IP Not From ARM or Synopsys
ARM and Synopsys are well-known physical IP companies however at DAC today I met with a lesser-known company named DXCORR that has some unique offerings for cache, multi-port memory and standard cell kicker libraries. I met with:… Read More
DAC 2012 – Sunday Night Kick Off
I arrived to a sunny San Francisco this afternoon, checked into my hotel then visited Moscone Center to pick up my Independent Media credentials. On the walk over I passed by Yerba Buena Gardens.… Read More
Two New Board Members at Mentor Graphics
One year ago the annual share holder meeting at Mentor Graphics had tight security, a no-camera policy, and the drama of Carl Icahn the corporate raider successfully adding three new board members. Fast forward to today where two of Icahn’s board members were not even nominated, and Mentor added two new board members. I chatted… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing