GenAI, the most talked-about manifestation of AI these days, imposes two tough constraints on a hardware platform. First, it demands massive memory to serve large language model with billions of parameters. Feasible in principle for a processor plus big DRAM off-chip and perhaps for some inference applications but too slow … Read More
Author: Bernard Murphy
Alphawave Semi Bridges from Theory to Reality in Chiplet-Based AI
Fault Sim on Multi-Core Arm Platform in China. Innovation in Verification
How much can running on a multi-core (Arm) CPU speed up fault simulation? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
The Innovation
Lifecycle Management, FuSa, Reliability and More for Automotive Electronics
Synopsys recently hosted an information rich-webinar, modestly titled “Improving Quality, FuSa, Reliability, and Security in Automotive Semiconductors”. I think they undersold the event; this was really about managing all of those things through the lifecycle of a car, in line with auto OEMs strategies for the future of the… Read More
Cadence Debuts Dynamic Duo III with a Basket of Goodies
I am a fan of product releases which bundle together multiple high-value advances. That approach reduces the frequency of releases (no bad thing) in exchange for more to offer per release, better proven through solid partner validation. The Dynamic Duo III release falls in this class, offering improvements in performance, capacity,… Read More
Managing Power at Datacenter Scale
That datacenters are power hogs is not news, especially now AI is further aggravating this challenge. I found a recent proteanTecs-hosted panel on power challenges in datacenter infrastructure quite educational both in quantifying the scale of the problem and in understanding what steps are being taken to slow growth in power… Read More
Arteris Frames Network-On-Chip Topologies in the Car
On the heels of Arm’s 2024 automotive update, Arteris and Arm announced an update to their partnership. This has been extended to cover the latest AMBA5 protocol for coherent operation (CHI-E) in addition to already supported options such as CHI-B, ACE and others. There are a couple of noteworthy points here. First, Arm’s new Automotive… Read More
Are Agentic Workflows the Next Big Thing in AI?
AI continues to be a fast-moving space and we’re always looking for the next big thing. There’s a lot of buzz now around something called agentic workflows – ugly name but a good idea. LLMs had a good run as the state-of-the-AI-art, however evidence is building that the foundation model behind LLMs alone has limitations, both theoretically… Read More
Arm Automotive Update Stresses Prototyping for Software Development
If you were at all uncertain about auto OEM development priorities, the answer is becoming clear: to accelerate/shift left automotive software development and debug. At 100M lines of code and accelerating, this task is overshadowing all others. A recent Arm update from Dipti Vachani (SVP and GM for the Automotive Line of Business)… Read More
Fault Simulation for AI Safety. Innovation in Verification
More automotive content 😀
In modern cars, safety is governed as much by AI-based functions as by traditional logic and software. How can these functions be fault-graded for FMEDA analysis? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO)… Read More
Simulating the Whole Car with Multi-Domain Simulation
Next significant automotive blog in a string I will be posting (see here for the previous blog).
In the semiconductor world, mixed simulation means mixing logic sim, circuit sim, virtual sim (for software running on the hardware we are designing) along with emulation and FPGA prototyping. While that span may seem all-encompassing,… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay