What XiangShan Got Right—And What It Didn’t Dare Try

What XiangShan Got Right—And What It Didn’t Dare Try
by Jonah McLeod on 08-12-2025 at 6:00 am
Categories: IP, RISC-V

An Open ISA, a Closed Mindset — Predictive Execution Charts a New Path

The RISC-V revolution was never just about open instruction sets. It was a rare opportunity to break free from the legacy assumptions embedded in every generation of CPU design. For decades, architectural decisions have been constrained by proprietary patents,… Read More

February 13, 2025February 12, 2025

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
by Jonah McLeod on 02-13-2025 at 6:00 am
Categories: IP, RISC-V

As RISC-V gains traction in the global semiconductor industry, developers are exploring fully open-source approaches to processor design. XiangShan, a high-performance RISC-V CPU project, combined with the Mulan Permissive License v2 (Mulan PSL v2), represents a community-driven, transparent alternative to proprietary… Read More

October 30, 2023October 31, 2023

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
by Daniel Nenni on 10-30-2023 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor. S7-19P not only accelerates the iterations of processor development but also simplifies other companies to realize … Read More