Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More