Tag: workshop

Semiconductor Traceability and Provenance Workshop

Semiconductor Traceability and Provenance Workshop
by Admin on 01-06-2026 at 7:15 pm

The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, January 27, 2026, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility, in Rockville, Maryland. This in-person, one-day event builds on the momentum from… Read More

Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications

Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications
by Admin on 10-15-2025 at 6:05 pm

This workshop is a fast-paced, one-day program led by Prof. Dragica Vasileska and Prof. Stephen M. Goodnick. Spend the morning grounding yourself in semiconductor physics and transport, then transition in the afternoon to instructor-led, hands-on Silvaco TCAD labs (e.g., MOS Capacitors, MOSFETs, SOI Devices, FinFETs).… Read More

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Chip-Package-System workshops

Chip-Package-System workshops
by Paul McLellan on 01-17-2012 at 4:30 pm
Categories: Ansys, Inc., EDA

Chips, packages and circuit boards (systems, hence CPS) used to be three separate domains with their own tools that barely interacted at all. If you were lucky, reassigning a pin on a package wouldn’t have to be done manually in all 3 places. But now, from a signal integrity, noise, power point of view these three domains must… Read More

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December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am
Categories: EDA, Siemens EDA

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More

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Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

Oct 27 – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 10-20-2011 at 9:56 am
Categories: EDA, Siemens EDA

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow

DRC Wiki

Graphical DRC vs Text-based DRC

Getting Real time Calibre DRC Results with Custom IC Editing

Transistor-level Electrical Rule Checking

Who Needs a 3D Field Solver for IC Design?

Prevention is Better… Read More