ESD Alliance Webinar: Gen-AI for Chip Design and Security

ESD Alliance Webinar: Gen-AI for Chip Design and Security
by Admin on 09-03-2026 at 1:47 am

This webinar will present a multi-agent intelligent assistant system architected to automate and augment SoC design and security verification.

Designing functionally correct, high-performance, and provably secure system-on-chips (SoCs) has become a strategic imperative for modern computing infrastructure. Yet traditional… Read More


Webinar: Deploy and Scale Your Simulation in the Cloud with Ansys, part of Synopsys, and AWS

Webinar: Deploy and Scale Your Simulation in the Cloud with Ansys, part of Synopsys, and AWS
by Admin on 09-03-2026 at 1:45 am

Learn how Ansys, part of Synopsys, and AWS enable engineering teams to deploy and scale simulation workloads in the cloud. Discover how cloud solutions such as Ansys Cloud Burst Compute deliver faster results, greater flexibility, and on-demand access to powerful compute resources.

Overview

Learn how Ansys, part of Synopsys,

Read More

Webinar: One TMR tech, two ways to sense: Infineon extends its TMR-based portfolio

Webinar: One TMR tech, two ways to sense: Infineon extends its TMR-based portfolio
by Admin on 09-03-2026 at 1:44 am

About the webinar

Infineon is extending its XENSIV™ magnetic sensing portfolio with tunnel magnetoresistance (TMR)-based sensors designed to help engineers achieve high-precision, low-noise and low-power magnetic sensing in compact systems. In this webinar, we will give designers a crisp overview of the latest TMR product

Read More

Webinar: Securing Software-Defined Vehicles with an Arm-Based Root of Trust

Webinar: Securing Software-Defined Vehicles with an Arm-Based Root of Trust
by Admin on 09-03-2026 at 1:43 am

As the automotive industry transitions to software-defined vehicles, security must evolve from a collection of isolated protections into a trusted foundation for the entire vehicle. Over-the-air updates, centralized compute architectures, vehicle connectivity, and increasingly autonomous functions are placing unprecedented… Read More


Webinar: From Copper to COUPE: Scaling AI Interconnects with Co-Packaged Optics

Webinar: From Copper to COUPE: Scaling AI Interconnects with Co-Packaged Optics
by Admin on 09-02-2026 at 10:37 pm

Featured Speakers:

  • Igor Elkanovich, CTO, GUC
  • Sheng-Fan Yang, Director, GUC
  • Madhumita Sanyal, Sr. Director Product Management, Synopsys

Co-packaged optics (CPO) breaks through the data movement constraint by moving optical engines next to the XPU, reducing electrical reach from centimeters to millimeters and delivering

Read More

Webinar: Shift Left on Warpage: Thermo-Mechanical Analysis Before the Design Locks

Webinar: Shift Left on Warpage: Thermo-Mechanical Analysis Before the Design Locks
by Admin on 09-02-2026 at 2:39 am

*Work Email Required for Registration*

For packaging, thermal, and mechanical engineers who need trusted warpage insight before stackup, material, and package architecture decisions are locked — and want to see what becomes possible when a full design study fits in an afternoon.

In advanced packaging, warpage is rarely a modeling… Read More


Webinar: Avestra – Assertion Driven Silicon Success

Webinar: Avestra – Assertion Driven Silicon Success
by Admin on 09-02-2026 at 2:36 am

COMPANY EMAIL REQUIRED FOR REGISTRATION.

Studies show that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration — work that remains largely manual today or is delegated to general-purpose LLMs that hallucinate more than 30% of the time and produce incorrect assertions.… Read More


Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation

Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation
by Mike Gianfagna on 09-01-2026 at 6:00 am

Follow the Money – Agentrys Raises $24.5 Million to Build Agentic Design Automation

Agentrys recently launched a new category of design technology, Agentic Design Automation (ADA). The approach promises to revolutionize AI deployment for chip design with technology that facilitates the building of targeted agentic design flows that get better with every run. There is a lot of information available on the … Read More


Webinar: Shift Left to Ship Faster: Verifying IP and SoCs at Real Workload Speeds

Webinar: Shift Left to Ship Faster: Verifying IP and SoCs at Real Workload Speeds
by Admin on 08-20-2026 at 11:40 pm

Featured Speakers:

  • Madhumita Sanyal, Sr. Director of Technical Product Management, Synopsys
  • Varun Agrawal, Director of Product Management, Synopsys

As SoC complexity climbs, traditional verification can’t keep pace — and system-level bugs surface late, when they’re hardest to fix. By pairing Hardware-Assisted… Read More


Webinar: High-Level Synthesis Summer Hackathon: From Python to High-Performance AI Accelerators

Webinar: High-Level Synthesis Summer Hackathon: From Python to High-Performance AI Accelerators
by Admin on 08-18-2026 at 8:52 pm

Designing AI inference hardware for edge applications often requires building custom hardware accelerated solutions to meet the demands for ultra-low power consumption and strict real-time response requirements. This webinar introduces Catapult™ AI NN, which provides an automated flow that starts with a Python neural… Read More