Semiconductor packaging is a critical step in the development of modern electronic devices, influencing their performance, reliability, and thermal management. The complexity of packaging technologies has grown significantly with the demand for miniaturization, higher power densities, and improved mechanical and thermal… Read More
This webinar will guide you through a modernized design process, covering everything to ensure a more comprehensive and accurate design. This includes:
Learn about the revolutionary AI-driven electromagnetic-aware methodology of Ansys that automates the optimization of the floor plan of analog and RF physical layouts.
DATE / TIME:
April 2, 2025
9 AM EDT / 3 PM CEST
Venue:
Virtual
Analog/RF IC design has been traditionally considered an art – sometimes even a “black art”
An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end RISC-V debug and trace solution consisting of embedded IPs and software that integrate with industry-standard tools.
We will… Read More
Join us on April 9 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.
Here’s What You Can Learn
How Embedded Data Management in Cadence Virtuoso Studio Supercharges Analog Design
Join us on April 8 to discover how to unlock the power of built-in data management using Keysight Design Data Management (SOS) within Cadence Virtuoso Studio.
Here’s What You Can Learn
The automotive industry has long evolved gradually—but 2024 proved to be anything but typical. With major automaker CEOs resigning and suppliers facing unexpected challenges, including a downturn in semiconductor demand despite increasing chip content per vehicle, the landscape
The ESD Alliance, a SEMI Technology Community, is hosting a webinar series, “Savage on Security,” moderated by Warren Savage, Researcher at University of Maryland, Applied Research Laboratory for Intelligence and Security.
Hardware is at the heart of computing systems. However, recent years have seen increased… Read More
Date: March, 13 – 9 a.m. PST
Using virtual prototypes alongside early accessible performance models of new SoC or Chiplet architectures has become the de facto standard for early architecture performance modeling, exploration, and analysis. However, as designs and tools become increasingly complex, these virtual
Debugging testbenches can be a time-intensive challenge, but modern tools provide advanced features to simplify and accelerate the process.
This webinar will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM
