3D ESD verification: Tackling new challenges in advanced IC design

3D ESD verification: Tackling new challenges in advanced IC design
by Admin on 12-17-2025 at 10:00 am

fig1 3d structures

By Dina Medhat

Three key takeaways

  • 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
  • Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation
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Double Patterning Verification

Double Patterning Verification
by Paul McLellan on 12-10-2012 at 3:03 am

You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.

Lithography is done using 193nm light. Today we use immersion… Read More