Does IDE Stand for Integrated Design Environment?

Does IDE Stand for Integrated Design Environment?
by Daniel Nenni on 12-21-2020 at 6:00 am

SemiWiki2 design 1

As regular readers may know, every few months I check in with Cristian Amitroaie, CEO of AMIQ EDA, to see what’s new with the company and their products. In our posts so far this year we’ve focused on verification, and now I’m wondering how an integrated development environment (IDE) provides benefits to designers. They work on huge… Read More


The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


Taking SystemVerilog Arrays to the Next Dimension

Taking SystemVerilog Arrays to the Next Dimension
by Admin on 05-27-2020 at 12:09 am

Register For This Web Seminar

Online – Jun 5, 2020
8:15 AM – 8:45 AM US/Pacific

Overview

Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types,

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WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING

WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING
by Admin on 05-26-2020 at 11:45 pm

Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.

The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS

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Debugging Hardware Designs Using Software Capabilities

Debugging Hardware Designs Using Software Capabilities
by Daniel Nenni on 12-20-2019 at 6:00 am

Every few months, I touch base with Cristian Amitroaie, CEO of AMIQ EDA, to learn more about how AMIQ is helping hardware design and verification engineers be more productive. Quite often, his answers surprise me. When he started describing their Design and Verification Tools (DVT) Eclipse Integrated Development Environment… Read More


Webinar: SystemVerilog Strategies

Webinar: SystemVerilog Strategies
by Daniel Payne on 07-04-2019 at 12:19 am

Hosted by Oasis Sales and Trilogic, Inc.

Overview

SystemVerilog (SV) has become the basis for verifying FPGA and ASIC designs.  As the complexity of SOC designs grows, advanced verification methodology concepts such as: Constrained Random Stimulus, Functional Coverage, and Test Environment Reuse are needed at the system … Read More


Renaming and Refactoring in HDL Code

Renaming and Refactoring in HDL Code
by Daniel Nenni on 02-12-2019 at 12:00 pm

I’ve enjoyed my past discussions with Cristian Amitroaie, the CEO of AMIQ EDA, in which we covered their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and their Verissimo SystemVerilog Testbench Linter. Cristian’s descriptions of AMIQ’s products and customers have intrigued me. They… Read More