As regular readers may know, every few months I check in with Cristian Amitroaie, CEO of AMIQ EDA, to see what’s new with the company and their products. In our posts so far this year we’ve focused on verification, and now I’m wondering how an integrated development environment (IDE) provides benefits to designers. They work on huge… Read More
Tag: systemverilog
The Polyglot World of Hardware Design and Verification
It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More
Taking SystemVerilog Arrays to the Next Dimension
Register For This Web Seminar
8:15 AM – 8:45 AM US/Pacific
Overview
Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types,
WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING
Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.
The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS
DVCon U.S.
The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification … Read More
Debugging Hardware Designs Using Software Capabilities
Every few months, I touch base with Cristian Amitroaie, CEO of AMIQ EDA, to learn more about how AMIQ is helping hardware design and verification engineers be more productive. Quite often, his answers surprise me. When he started describing their Design and Verification Tools (DVT) Eclipse Integrated Development Environment… Read More
Webinar: SystemVerilog Strategies
Hosted by Oasis Sales and Trilogic, Inc.
Overview
SystemVerilog (SV) has become the basis for verifying FPGA and ASIC designs. As the complexity of SOC designs grows, advanced verification methodology concepts such as: Constrained Random Stimulus, Functional Coverage, and Test Environment Reuse are needed at the system … Read More
Renaming and Refactoring in HDL Code
I’ve enjoyed my past discussions with Cristian Amitroaie, the CEO of AMIQ EDA, in which we covered their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and their Verissimo SystemVerilog Testbench Linter. Cristian’s descriptions of AMIQ’s products and customers have intrigued me. They… Read More
Design Integrity Investment Thesis Part 2
It is important when talking about a market to first establish the need and potential growth, then determine how the market is being served. This requires examining product features and services offered. … Read More
Verifying a RISC-V in 1 Page of Code!
This is it! This is the single page of code that Ákos Hadnagy wrote this summer to formally verify WARP-V, an open-source RISC-V CPU core.… Read More