Power Modeling and Simulation of System Memory Subsystem

Power Modeling and Simulation of System Memory Subsystem
by Daniel Payne on 07-24-2014 at 11:05 am

One great benefit of designing at the ESL level is the promise of power savings on the order of 40% to 70% compared to using an RTL approach. Since a typical SoC can contain a hierarchy of memory, this kind of power savings could be a critical factor in meeting PPA goals. To find out how an SoC designer could use such an ESL approach to power… Read More