TSMC ♥ Mentor (Calibre PERC)

TSMC ♥ Mentor (Calibre PERC)
by Daniel Nenni on 10-29-2013 at 8:00 am

As semiconductors become more integrated into our lives reliability is becoming a critical issue. As IP consumes more of our die, IP reliability is becoming a critical issue. As we pack more transistors into a chip, reliability is becoming a critical issue. As we move from 28nm to 20nm to 16nm, reliability is becoming a critical … Read More


Fabless to OIP

Fabless to OIP
by Paul McLellan on 04-10-2013 at 7:22 pm

Suk Lee drew the short straw at the TSMC Symposium yesterday, with the 5pm slot. Not only late in the day but between all the attendees and free beer. The morning sessions had been standing room only, with several hundred standees (as they call them on muni around here, but isn’t a standee really someone being stood on?). But … Read More


Fast Track Seminars

Fast Track Seminars
by Paul McLellan on 09-15-2011 at 6:11 pm


Atrenta’s SoC realization seminars, “Fast Track Your SoC Design” have started.The first one was in Ottowa last Tuesday, and it was a full house. In a straw poll, most of the attendees acknowledged facing IP handoff and quality issues. The keynote speaker was Dr Yuejian Wu, director of ASIC development at Infinera… Read More