Podcast EP299: The Current and Future Capabilities of Static Verification at Synopsys with Rimpy Chugh

Podcast EP299: The Current and Future Capabilities of Static Verification at Synopsys with Rimpy Chugh
by Daniel Nenni on 07-25-2025 at 10:00 am

Dan is joined by Rimpy Chugh, a Principal Product Manager at Synopsys with 14 years of varied experience in EDA and functional verification. Prior to joining Synopsys, Rimpy held field applications and verification engineering positions at Mentor Graphics, Cadence and HCL Technologies.

Dan explores the expanding role of static… Read More


The Problem with Reset Domain Crossings

The Problem with Reset Domain Crossings
by Bernard Murphy on 05-14-2020 at 6:00 am

Reset button

Design complexities in reset, like everything else in big SoC designs, has become incredibly complex, for all sorts of reasons. Long, long ago reset was something you just did once, when you turned the power on. Turn on, then hold reset for some amount of time until everything is in a known starting state, and off you go. Nice and simple.… Read More


Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am

Faults

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More


Low Power Verification Shifting Left

Low Power Verification Shifting Left
by Bernard Murphy on 05-08-2018 at 11:00 pm

I normally think of shift left as a way to move functional verification earlier in design, to compress the overall design cycle. But it can also make sense in other contexts, one particularly important example being power intent verification.

If you know anything about power intent, you know that it affects pretty much all aspects… Read More