Don’t Shoot Yourself in the Foot With Timing Exceptions

Don’t Shoot Yourself in the Foot With Timing Exceptions
by Paul McLellan on 08-15-2013 at 1:42 pm

Timing exceptions are ways of guiding design tools, primarily synthesis and static timing analysis (STA), but these days also place & route and perhaps other tools. Most paths in a design go from one register to the next register. Both registers are on the same clock, and the design needs to ensure that the signal can make it from… Read More


Global Design Closure

Global Design Closure
by Paul McLellan on 01-09-2013 at 8:34 pm

Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.


SoCs are really put together in two … Read More


RTL Power Models

RTL Power Models
by Paul McLellan on 11-08-2011 at 8:00 am

One of the challenges of doing a design in the 28nm world is that everything depends on everything else. But some decisions need to be made early with imperfect information. But the better the information we have, the better those early decisions will be. One area of particular importance is selecting a package, designing a power… Read More