Verification is always a top priority for any chip project. Re-spins result in lost time-to-market and significant cost overruns. Chip bugs that make it to the field present another level of lost revenue, lost brand confidence and potential costly litigation. If the design is part of the avionics or control for an aircraft, the… Read More
![[white paper] Parasitic Analysis Figures](https://semiwiki.com/wp-content/uploads/2025/10/Fig1-net-level-visualization-150x127.jpg)
By Omar Elabd
As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More
Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC… Read More
Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More
On July 9, 2025, Michael Munsey, VP of Semiconductor Industry at Siemens, and Vishal Moondhra, VP of Solutions at Perforce, presented a DACtv session announcing their strategic partnership, as seen in the YouTube video. This collaboration integrates Siemens’ digital twin and digital thread technologies with Perforce’s version… Read More
On July 18, 2025, Siemens EDA and Nvidia presented a compelling vision for the future of electronic design automation (EDA) at a DACtv event, emphasizing the transformative role of artificial intelligence (AI) in semiconductor and PCB design. Amit Gupta, Vice President and General Manager at Siemens EDA, and John Lynford, head… Read More
The demand for higher performance, greater configurability, and more cost-effective solutions is pushing the industry toward heterogeneous integration and 3D integrated circuits (3D ICs). These solutions are no longer reserved for niche applications—they are rapidly becoming essential to mainstream semiconductor design.… Read More
By Hossam Sarhan
Communication has become the backbone of our modern world, driving the rapid growth of the integrated circuit (IC) industry, particularly in communication and automotive applications. These applications have increased the demand for high-performance analog and radio frequency (RF) designs.
However, designing… Read More
By Mark Tawfik
Parasitic extraction is essential in integrated circuit (IC) design, as it identifies unintended resistances, capacitances, and inductances that can impact circuit performance. These parasitic elements arise from the layout and interconnects of the circuit and can affect signal integrity, power consumption,… Read More
In the race to deliver ever-larger SoCs under shrinking schedules, simulation is becoming a bottleneck. With debug cycles constrained by long iteration times—even for minor code changes—teams are finding traditional flows too rigid and slow. The problem is further magnified in continuous integration and continuous deployment… Read More
