Challenges of 20nm IC Design

Challenges of 20nm IC Design
by Daniel Payne on 04-29-2013 at 11:38 am

Designing at the 20nm node is harder than at 28nm, mostly because of the lithography and process variability challenges that in turn require changes to EDA tools and mask making. The attraction of 20nm design is realizing SoCs with 20 billion transistors. Saleem Haider from Synopsys spoke with me last week to review how Synopsys… Read More