Unlocking the Future: Join Us at RISC-V Con 2024 Panel Discussion!

Unlocking the Future: Join Us at RISC-V Con 2024 Panel Discussion!
by Daniel Nenni on 06-03-2024 at 10:00 am

Software Panel pix (1)

Are you ready to dive into the heart of cutting-edge computing? RISC-V Con 2024 is just around the corner, and we’re thrilled to invite you to a riveting panel discussion that promises to reshape your understanding of advanced computing. On June 11th, from 4:00 to 5:00 PM, at the prestigious DoubleTree Hotel in San Jose, California,… Read More


Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems

Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems
by Mike Gianfagna on 06-03-2024 at 6:00 am

Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems

Synopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a recent in-depth article on the make-up of the ARC-V family on SemiWiki here. This is important and impactful news; I encourage you to read these articles if you haven’t… Read More


CEO Interview: Roger Espasa of Semidynamics

CEO Interview: Roger Espasa of Semidynamics
by Daniel Nenni on 05-17-2024 at 6:00 am

Roger Espasa

Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence. Prior to the foundation of the company, Roger was Technical Director/Distinguished… Read More


Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks

Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber Attacks
by Daniel Nenni on 05-10-2024 at 8:00 am

EW Award 24 Logo winner safety Security coloured RGB 300dpi 960x117

Most organizations are aware of cybercrime attempts such as phishing, installing malware from dodgy websites or ransomware attacks and undertake countermeasures. However, relatively little attention has been given to memory safety vulnerabilities such as buffer overflows or over-reads. For decades, the industry has created… Read More


An Enduring Growth Challenge for Formal Verification

An Enduring Growth Challenge for Formal Verification
by Bernard Murphy on 05-08-2024 at 6:00 am

Math blackboard min

A high-quality verification campaign including methods able to absolutely prove the correctness of critical design behaviors as a complement to mainstream dynamic verification? At first glance this should be a no-brainer. Formal verification offers that option and formal adoption has been growing steadily, now used in around… Read More


Enhancing the RISC-V Ecosystem with S2C Prototyping Solution

Enhancing the RISC-V Ecosystem with S2C Prototyping Solution
by Daniel Nenni on 04-11-2024 at 6:00 am

ChipLink

RISC-V’s popularity stems from its open-source framework, enabling customization, scalability, and mitigating vendor lock-in. Supported by a robust community, its cost-effectiveness and global adoption make it attractive for hardware innovation across industries.

Despite its popularity, evolving RISC-V architectures… Read More


LIVE WEBINAR: RISC-V Instruction Set Architecture: Enhancing Computing Power

LIVE WEBINAR: RISC-V Instruction Set Architecture: Enhancing Computing Power
by Daniel Nenni on 03-29-2024 at 8:00 am

RISC V Banner SemiWiki

In the dynamic landscape of chip design, two trends stand out as game-changers: the rise of the RISC-V instruction set architecture (ISA) and the advent of Software Defined products. Today, we delve into why these trends are not just shaping the industry but propelling companies like Andes and Menta to the forefront of innovation.… Read More


Andes Technology: Pioneering the Future of RISC-V CPU IP

Andes Technology: Pioneering the Future of RISC-V CPU IP
by Frankwell Lin on 03-25-2024 at 6:00 am

Table 1

On September 13, 2021, Andes Technology Corporation successfully issued its GDR (Global Depositary Receipt) public offering on the Luxembourg Stock Exchange. At the time it made Andes the only international public RISC-V Instruction set architecture (ISA) CPU IP supplier. This allowed investors around the world to participate… Read More


Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez

Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez
by Daniel Nenni on 03-15-2024 at 10:00 am

Dan is joined by Matt Gutierrez. Matt joined Synopsys in 2000 and is currently Sr. Director of Marketing for Processor & Security IP and Tools. His current responsibilities include the worldwide marketing of ARC Processors and Subsystems, Security IP, and tools for the development of application-specific instruction … Read More


Arteris is Unleashing Innovation by Breaking Down the Memory Wall

Arteris is Unleashing Innovation by Breaking Down the Memory Wall
by Mike Gianfagna on 03-14-2024 at 6:00 am

Arteris is Unleashing Innovation by Breaking Down the Memory Wall

There is a lot of discussion about removing barriers to innovation these days. Semiconductor systems are at the heart of unlocking many forms of technical innovation, if only we could address issues such as the slowing of Moore’s Law, reduction of power consumption, enhancement of security and reliability and so on. But there … Read More