Tag: RISC-V verification

Posted on

Systematic RISC-V architecture analysis and optimization

Systematic RISC-V architecture analysis and optimization
by Don Dingee on 08-28-2023 at 10:00 am
Categories: Prototyping, S2C EDA

RISC V architecture analysis and optimization chain

The RISC-V movement has taken off so quickly because of the wide range of choices it offers designers. However, massive flexibility creates its own challenges. One is how to analyze, optimize, and verify an unproven RISC-V core design with potential microarchitecture changes allowed within the bounds of the specification. … Read More

Posted on

Maven Silicon’s RISC-V Processor IP Verification Flow

Maven Silicon’s RISC-V Processor IP Verification Flow
by Sivakumar PR on 02-24-2023 at 6:00 am
Categories: IP, Maven Silicon, RISC-V, Semiconductor Services

1 1

RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized accelerators and optional standard extensions to support general-purpose software development. RISC-V supports both 32-bit and … Read More