Webinar: Unlocking Next-Generation Performance for CNNs on RISC-V CPUs

Webinar: Unlocking Next-Generation Performance for CNNs on RISC-V CPUs
by Daniel Nenni on 02-13-2025 at 10:00 am

image002 (2)

The growing demand for high-performance AI applications continues to drive innovation in CPU architecture design. As machine learning workloads, particularly convolutional neural networks (CNNs), become more computationally intensive, architects face the challenge of delivering performance improvements while maintaining… Read More


An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2

An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
by Jonah McLeod on 02-13-2025 at 6:00 am

PastedGraphic 1

As RISC-V gains traction in the global semiconductor industry, developers are exploring fully open-source approaches to processor design. XiangShan, a high-performance RISC-V CPU project, combined with the Mulan Permissive License v2 (Mulan PSL v2), represents a community-driven, transparent alternative to proprietary… Read More


Podcast EP273: An Overview of the RISC-V Market and CAST’s unique Abilities to Grow the Market with Evan Price

Podcast EP273: An Overview of the RISC-V Market and CAST’s unique Abilities to Grow the Market with Evan Price
by Daniel Nenni on 02-07-2025 at 10:00 am

Dan is joined by Evan Price, Product Manager for embedded processors at CAST. Evan has had a diverse and successful 15-year career developing, then leading as project manager and director, with a variety of semiconductor-based products. Evan joined CAST in 2024 and provides technical support as well as handling product marketing… Read More


2025 Outlook with Volker Politz of Semidynamics

2025 Outlook with Volker Politz of Semidynamics
by Daniel Nenni on 02-06-2025 at 6:00 am

Paul Volker Semidynamics SemiWiki

Tell us a little bit about yourself and your company. 

I am the Chief Sales Officer and I lead the global sales team and drive the overall sales process.

Semidynamics was founded 2016 as a design service company with a focus on RISC-V. This was so successful that the CEO decided to pivot the company towards its own IP sales and started… Read More


CEO Interview: With Fabrizio Del Maffeo of Axelera AI

CEO Interview: With Fabrizio Del Maffeo of Axelera AI
by Daniel Nenni on 01-31-2025 at 6:00 am

Fabrizio Del Maffeo CEO Co Founder (1)

Fabrizio Del Maffeo is the CEO and co-founder of Axelera AI, the Netherlands-based startup building game-changing, scalable hardware for AI at the edge. Axelera AI was incubated by the Bitfury Group, a globally recognised emerging technologies company, where Fabrizio previously served as Head of AI. In his role at Axelera AI,… Read More


Automating Formal Verification

Automating Formal Verification
by Daniel Payne on 01-30-2025 at 10:00 am

LUBIS on cloud min

Formal verification methods are being adopted at a fast pace as a complement to traditional verification methods like functional simulation for IP blocks in SoC designs. I had a video meeting with Max Birtel, co-founder of LUBIS EDA and learned more about their history, products and vision. This company started recently in 2020… Read More


How I learned Formal Verification

How I learned Formal Verification
by Daniel Nenni on 12-11-2024 at 10:00 am

Bing Xue

Bing Xue is a dedicated Formal Verification Engineer at Axiomise, with a strong academic and professional foundation in hardware verification. He completed his PhD at the University of Southampton, where he conducted cutting-edge research on Formal Verification, RISC-V, and the impact of Single Event Upsets. Bing is … Read More


Relationships with IP Vendors

Relationships with IP Vendors
by Daniel Nenni on 11-21-2024 at 10:00 am

Semiwiki Blog Post #3 Image #2

An animated panel discussion Design Automation Conference in June offered up a view of the state of RISC-V and open-source functional verification and a wealth of good material for a three-part blog post series.

Parts One and Two covered a range of topics from microcontroller versus more general-purpose processor versus running… Read More


Changing RISC-V Verification Requirements, Standardization, Infrastructure

Changing RISC-V Verification Requirements, Standardization, Infrastructure
by Daniel Nenni on 11-07-2024 at 10:00 am

Abstract,Futuristic,Infographic,With,Visual,Data,Complexity,,,Represent,Big

A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

In Part Two, moderator Ron Wilson and Contributing Editor … Read More


Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution

Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution
by Kalar Rajendiran on 11-07-2024 at 6:00 am

Risc V CPU

Founded with a vision to create transformative, customizable IP solutions, Semidynamics has emerged as a significant player in the AI hardware industry. Initially operating as a design engineering company, Semidynamics spent its early years exploring various pathways before pivoting to develop proprietary intellectual… Read More