RISC-V Summit North America 2027 is taking place from February 16 to 18 at the Hyatt Regency, Embarcadero in San Francisco, California. February 16 is Member Day and the main conference will begin on February 17.
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. SHD Group estimates
Lisa Spelman is CEO of Cornelis, where she leads the company’s efforts to advance high-performance networking for AI and HPC infrastructure. She brings more than 20 years of experience across AI, cloud, enterprise infrastructure, data center operations, product strategy, and go-to-market leadership.
Before joining Cornelis,… Read More
Semiconductor designers today face a critical hurdle: how to smoothly transition from an open-source hardware blueprint to a commercially hardened, production-ready silicon implementation. As semiconductors play an increasingly essential role in powering the AI era, safeguarding these hardware foundations has become… Read More
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Join us in person for an exciting opportunity to dive deep into RISC-V performance optimization! Whether you’re a developer, engineer, or just a tech enthusiast, this
While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More
RISC-V Summit China 2026 will take place from October 18 to 20, 2026 at the Shenzhen Convention & Exhibition Center (Futian). As an important annual gathering for global open hardware and the RISC-V ecosystem, this Summit will bring together leading scientists, core architects, industry executives, technology developers,… Read More
RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More
Hot Chips 2026, formally the thirty-eighth Symposium on High Performance Chips, arrives at Stanford’s Memorial Auditorium from August 23 through 25 with a program that captures a decisive shift in computer architecture. Peak arithmetic throughput remains important, but the conference is increasingly about system balance:… Read More
AI was everywhere at DAC 2026, so I stopped by the booth of Rise Design Automation to chat with Ellie Burns to hear what’s new this year. Ellie shared that Rise DA has added a new AI-powered flow to go from specification to a High Level Synthesis (HLS) model, to a RTL model. The reason for using a HLS model is to gain much more simulation… Read More
Daniel is joined by David Kravitz, Senior Principal Engineer at SiFive, the pioneer of the RISC- V computing revolution. A veteran silicon architect with decades of experience designing high-performance processors ranging from VAX and Alpha to MIPS and ARM, David led the team behind some of the most critical breakthroughs in… Read More
