In the race to power ever-larger AI models, raw compute is only half the battle. The real challenge lies in moving massive datasets between processors, accelerators, and memory at speeds that keep up with trillion-parameter workloads. Synopsys tackles this head-on with its webinar, How PCIe Multistream Architecture is Enabling… Read More
Tag: pcie
Webinar: How PCIe Multistream Architecture is enabling AI Connectivity at 64 GT/s and 128 GT/s
Featured Speakers:
- Diwakar Kumaraswamy, Sr. Staff Technical Product Manager, Synopsys
AI and HPC workloads push fabric speeds to deliver higher parallelism and utilization at extreme data rates. To support these higher rates, the controller architecture needs to be completely redefined resulting in the new PCIe controller
Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?
Synopsys recently held a webinar session on this topic and Gustavo Pimentel, Principal Product Marketing Manager at the company led the webinar session. Going into the webinar session, I found myself wondering: why focus on PCIe 5.0, eight years after its release? With the industry buzzing about Edge AI, cloud computing, and … Read More
Smart Verification for Complex UCIe Multi-Die Architectures
By Ujjwal Negi – Siemens EDA
Multi-die architectures are redefining the limits of chip performance and scalability through the integration of multiple dies into a single package to deliver unprecedented computing power, flexibility, and efficiency. At the heart of this transformation is the Universal Chiplet Interconnect… Read More
Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?
Featured Speakers:
- Gustavo Pimentel, Principal Product Marketing Manager, Synopsys
As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling
PCI-SIG Developers Conference Korea 2025
PCI-SIG is returning to Seoul, South Korea on September 22, 2025. Members of the PCI-SIG community including systems architects, designers, engineers, and engineering managers are all invited to attend this fantastic event.
Overview
PCI-SIG Developers Conferences are free events for our 900+ member companies that… Read More
AI Booming is Fueling Interface IP 23.5% YoY Growth
AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system need to be interconnected with ever more bandwidth and lower latency, creating the need for ever advanced protocol… Read More
Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management
Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many… Read More
Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques
In today’s digital landscape, data security has become an indispensable feature for any data transfer protocol, including Peripheral Component Interconnect Express (PCIe). With the rising frequency and sophistication of digital attacks, ensuring data integrity, confidentiality, and authenticity during PCIe transport… Read More
Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively… Read More
