Webinar: Latest Innovations and Updates in ASICs with Efabless!

Webinar: Latest Innovations and Updates in ASICs with Efabless!
by Admin on 11-15-2023 at 3:48 pm

Description

In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%.

Topics Include:

– OpenFrame – a new version of Caravel that gives 50% more area

– GPIO configuration… Read More


The Efabless Generative AI Challenges and Why They Matter

The Efabless Generative AI Challenges and Why They Matter
by Daniel Nenni on 07-20-2023 at 10:00 am

Efabless Banner for SemiWiki

Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series.  As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create… Read More


Virtual Training Workshop: Advanced Physical Design using OpenLANE/Sky130

Virtual Training Workshop: Advanced Physical Design using OpenLANE/Sky130
by Admin on 07-25-2022 at 2:37 pm

Physical Design or PnR (Place and Route) is the core of any IC design cycle. From a RTL netlist to final tape-out, each phase of PnR brings it’s own challenges and surprises. “What are these challenges?” “What is the process?” “Can I build a chip of my own?”- If you have these questions and if you are eager to delve into the world of ASIC

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