SIP Modules Solve Numerous Scaling Problems – But Introduce New Issues

SIP Modules Solve Numerous Scaling Problems – But Introduce New Issues
by Tom Simon on 01-27-2022 at 10:00 am

SIP Verification

Multi-chip modules are now more important than ever, even though the basic concept has been around for decades. With The effects of Moore’s Law and other factors such as yield, power, and process choices, reasons for dividing what once would have been a single SOC into multiple die and integrating them in a single module have become… Read More


High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by admin on 06-27-2020 at 4:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential
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eSilicon White Paper on Chiplets – Good Read

eSilicon White Paper on Chiplets – Good Read
by Randy Smith on 10-17-2019 at 10:00 am

eSilicon recently released a paper detailing its experiences and its thoughts on the future of chiplets. The author of the white paper is Dr. Carlos Macián. I have also covered a presentation given by Carlos recently at the AI Hardware Summit, and he is well-spoken and quite knowledgeable. To get the white paper, go to the eSiliconRead More


A Comprehensive Power Analysis Solution for SoC+Package

A Comprehensive Power Analysis Solution for SoC+Package
by Pawan Fangaria on 09-08-2014 at 4:00 pm

Since power has become a critical factor in semiconductor chip design, the stress is towards decreasing supply voltage to reduce power consumption. However, the threshold voltage to switch devices cannot go down beyond a certain limit and these results in an extremely narrow margin for noise between the two. And that gets further… Read More