Jasper’s DAC Program

Jasper’s DAC Program
by Paul McLellan on 05-28-2013 at 3:52 pm

Jasper’s booth is 2346 where you can see demos of the JasperGold Apps and attend seminars on the experiences of ST and Broadcom, and others:

  • The Broadcom presentation on making formal an integral part of chip design is Tuesday at 10am.
  • The ST presentation on adapting formal methods in ARM subsystems is Monday at 1.30pm and
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Cavium Adopts JasperGold Architectural Modeling

Cavium Adopts JasperGold Architectural Modeling
by Paul McLellan on 03-05-2013 at 7:00 am

Cavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.

Cavium have… Read More


Catch Jasper at SemiIsrael Verification Day and at DVCon 2013

Catch Jasper at SemiIsrael Verification Day and at DVCon 2013
by Paul McLellan on 01-30-2013 at 4:08 pm

Jasper is presenting at both ends of the world at both ends of February.

First in Israel, it is SemiIsrael Verification Day 2013 on February 5th (next Tuesday) at Green House in Tel Aviv.

  • Zihad Hanna, VP of Research and Chief Architect and General Manager of Jasper Israel will be talking about Security Formal Verification of Hardware
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Formal Verification at ARM

Formal Verification at ARM
by Paul McLellan on 12-20-2012 at 4:34 pm

There are two primary microprocessor companies in the world these days: Intel and ARM. Of course there are many others but Intel is dominant on the PC desktop (including Macs) and ARM is dominant in mobile (including tablets).

One of the keynotes at last month’s Jasper User Group (JUG, not the greatest of acronyms) was by Bob… Read More