In Low Voltage Timing, the Center Cannot Hold

In Low Voltage Timing, the Center Cannot Hold
by Bernard Murphy on 01-25-2016 at 7:00 am

When I started discussing this topic with Isadore Katz, I was struggling to find a simple way to Image Removedexplain what he was telling me – that delay and variance calculations in STA tools are wrong at low voltage because the average (the center) of a timing distribution shifts from where you think it is going to be. He told me that… Read More


The Revenge of Microprocessor Design: The Return of the Macro

The Revenge of Microprocessor Design: The Return of the Macro
by Bernard Murphy on 11-05-2015 at 12:00 pm

(Two Star Wars™ allusions in one title – eat your heart out George Lucas.) Most of us are comfortable with the idea that you design more or less whatever you want in RTL and let the synthesis tool pick logic gates to implement that functionality. Sure it may need a little guidance here and there but otherwise synthesis is more or less … Read More