How Sonics Uses Jasper Formal Verification

How Sonics Uses Jasper Formal Verification
by Paul McLellan on 11-11-2014 at 7:00 am

The Jasper part of Cadence announced jointly with Sonics a relationship whereby Sonics uses JasperGold Apps as part of their verification. I talked to Drew Wingard, the CTO, about how they use it.

One way is during the day when their design engineers use Jasper as part of their verification arsenal. Interestingly it is the design… Read More


Cadence Acquires Jasper

Cadence Acquires Jasper
by Paul McLellan on 04-21-2014 at 4:06 pm

Image RemovedCadence announced today that it is acquiring Jasper Design Automation for $170M in an all-cash offer. Jasper has $24M in cash so it is really an acquisition for around $145M. i think that is around 4X revenue but I only know rumors about Jasper’s revenue numbers.

All the big 3 already have their own formal technology… Read More


Kathryn: "Formal Will Dominate Verification"

Kathryn: "Formal Will Dominate Verification"
by Paul McLellan on 10-23-2013 at 4:16 pm

At the Jasper Users’ Group meeting, Kathryn presented the state of Jasper. The numbers are impressive. The company has grown at a CAGR of over 35% since 2007, which is 6 times faster than EDA as a whole. They have been profitable at 15-20% EBITDA for 14 consecutive quarters.
Image Removed
Jasper is focused on engaging deeply… Read More


LSI’s Experience With Formality Ultra

LSI’s Experience With Formality Ultra
by Paul McLellan on 08-26-2013 at 5:36 pm

Image RemovedLSI is an early adopter of Formality Ultra, Synopsys’s tool for improving the entire ECO flow. I already wrote about the basic capability of the tool here. ECOs are changes that come very late in the design cycle, after place and route has already been “nearly” completed. They occur either due to… Read More


Jasper: Negronis on tap

Jasper: Negronis on tap
by Paul McLellan on 08-22-2013 at 6:26 pm

Did you know that Jasper’s Corner Tap in San Francisco serves Negronis on tap? It’s true. They also have Hanky Panky on tap, which is a Negroni with the Campari replaced with Fernet (which everyone pronounces as Frenet despite it being…well…wrong). And here’s another thing you probably didn’t… Read More


What Do Brazil and Sweden Have in Common?

What Do Brazil and Sweden Have in Common?
by Paul McLellan on 08-06-2013 at 4:55 pm

Well, Sweden is not noted for its carnivals, Brazil is not noted for it’s tall blonde blue-eyed women, Sweden’s climate is not great for growing sugar cane and Brazil’s isn’t great for reindeer. Both countries speak languages with odd-sounding vowels but they are not the same language. But, ding, Jasper… Read More


Formality Ultra, Streamline Your ECOs

Formality Ultra, Streamline Your ECOs
by Paul McLellan on 06-17-2013 at 8:00 am

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes… Read More


Jasper Low Power Verification App

Jasper Low Power Verification App
by Paul McLellan on 05-14-2013 at 1:58 am

Image RemovedToday, Jasper announced their new Jasper-Gold Low Power Verification App. This is focused on verifying low power designs with multiple power domains, voltage islands, power shutoff, clock shutoff, and all the other techniques used for reducing power. Of course power is the main driver of SoC design these days, … Read More


Integrating Formal Verification into Synthesis

Integrating Formal Verification into Synthesis
by Paul McLellan on 03-05-2013 at 1:29 pm

Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. But designs are getting very large and formal verification is a complex tool to use, especially if the design is too large for the formal tool… Read More


Cavium Adopts JasperGold Architectural Modeling

Cavium Adopts JasperGold Architectural Modeling
by Paul McLellan on 03-05-2013 at 7:00 am

Image RemovedCavium designs some very complex SoCs containing multiple ARM or MIPS cores at 32 and 64 bit. This complexity leads to major challenges in validating the overall chip architecture to ensure that their designs will meet the requirements of their customers once they are completed, with performance as high as 100Gbps.… Read More