Verifying Finite State Machines

Verifying Finite State Machines
by Paul McLellan on 09-10-2012 at 2:05 pm

Finite state machines (FSMs) are a very convenient way of describing certain kinds of behavior. But like any other aspect of design, it is important to get everything right. Since finite state machines have been formally studied, there is a lot of knowledge about the types of bugs that a finite state machine might exhibit.

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