By Mark Tawfik
Overview: Protecting ICs from costly ESD and latch-up failures
Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].
Ensuring the robust protection of integrated circuits (ICs) against various… Read More
November 4, 2025 | 10:00 AM PST
This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that goes beyond simple k-factor analysis. The methods will be demonstrated using Qorvo GaN technology and related non-linear models that have
By Zameer Mohammed
This article claims to provide clear key insights of Min Pulse Width (MPW) timing signoff check, proactive closure strategies for faster time-to-market, and effective methods to prevent silicon failures.
Min Pulse Width (MPW) check for timing signoff has become an important design constraint at the sub-5nm… Read More
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL,
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines… Read More
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater.
Join this webinar to see how the Veloce™ hardware-assisted verification… Read More
As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We… Read More
The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test, and manufacturing
Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet.
This webinar is designed for technical engineers tasked with defining and implementing solutions for power management, power monitoring, and power quality within data center power supply systems.
Explore the world of Electrical Power Management Systems
