Nagesh has built a career spanning multiple aspects of system design and development at companies including Hewlett-Packard, Cadence, Xilinx, and Lattice Semiconductor.
He is also a serial entrepreneur. Nagesh founded Taray, Inc., which developed memory interface generators for Xilinx designs and was later acquired by … Read More
The 2026 Design Automation Conference (DAC 2026) marks another pivotal moment for the semiconductor and electronic systems industry as artificial intelligence, chiplets, heterogeneous integration, and system-level optimization redefine the future of design automation. Held July 26–29, 2026, at the Long Beach Convention… Read More
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Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.
In this webinar, we will demonstrate… Read More
“How Will Agentic AI Change Chip Design and Verification?” features EDA and emerging agentic AI company executives and entrepreneurs discussing changes within chip design and verification as agentic AI tools become more mainstream. Panelists will distill the excitement surrounding the innovation in chip design and verification,… Read More
As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional… Read More
AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests.
Join Ram Periakaruppan, vice president and general manager of network applications and security at… Read More
As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits.
Join Jun Chie, Vice President of Product Management at Keysight,… Read More
Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.
Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight,… Read More
Wednesday, March 11 – 8:00 AM Pacific
Design and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation, they need protocol accuracy from day one, and they need a predictable path to signoff while integration … Read More
Siemens has strengthened its position in EDA and manufacturing by acquiring ASTER Technologies, a specialist in test and reliability solutions for printed circuit boards. The acquisition represents a strategic step in Siemens’ broader vision to deliver a fully integrated, end-to-end digital thread for electronics design,… Read More
