Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


Webinar: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation Tools

Webinar: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation Tools
by Admin on 10-08-2025 at 9:51 pm

November 4, 2025 | 10:00 AM PST

This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that goes beyond simple k-factor analysis. The methods will be demonstrated using Qorvo GaN technology and related non-linear models that have

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MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design

MIN PULSE WIDTH (MPW) TIMING CHECK The Silent Timing Trap Lurking in Every Sub-5nm Design
by Admin on 10-05-2025 at 10:00 am

pic1

By Zameer Mohammed

This article claims to provide clear key insights of Min Pulse Width (MPW) timing signoff check, proactive closure strategies for faster time-to-market, and effective methods to prevent silicon failures.

Min Pulse Width (MPW) check for timing signoff has become an important design constraint at the sub-5nmRead More


Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis
by Admin on 09-24-2025 at 4:37 pm

The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL,

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Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System
by Admin on 09-23-2025 at 3:34 pm

As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines… Read More


Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet

Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet
by Admin on 09-22-2025 at 4:36 pm

Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater.

Join this webinar to see how the Veloce™ hardware-assisted verification… Read More


Webinar: Hardware design of custom AI accelerators using High-Level Synthesis

Webinar: Hardware design of custom AI accelerators using High-Level Synthesis
by Admin on 09-04-2025 at 1:32 am

As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We… Read More


Webinar: 448G PAM4: The Future of 3.2T Data Centers

Webinar: 448G PAM4: The Future of 3.2T Data Centers
by Admin on 08-27-2025 at 8:13 pm

About this event

Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet.

Who should attend this event?

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Webinar: Powering Data Centers for the Future

Webinar: Powering Data Centers for the Future
by Admin on 08-27-2025 at 8:07 pm

SICAM EPMS the future proven Solution for Power Management in Data Center

This webinar is designed for technical engineers tasked with defining and implementing solutions for power management, power monitoring, and power quality within data center power supply systems.

Explore the world of Electrical Power Management Systems

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