Please join us at the Design Automation Conference 2025 where we will highlight the company’s wide range of EDA products and semiconductor IP targeting, Power Devices, Automotive, Memory, Displays, HPC, 5G / 6G, and IoT applications.
When: June 23 – 25, 2025, Exhibit Hours: 10:00 AM PDT – 6:00 PM PDT
Where: Moscone Center West,… Read More
June 24, 2025
12:00 PM -1:00 PM
Moscone West | San Francisco, CA
Calibre: Supercharge your chip integration efforts
Siemens is excited to host an exclusive event for our customers at the Design Automation Conference
Join us at DAC for lunch and learn how our new products can supercharge your chip integration efforts:
– Chip… Read More
Overview of the design of today’s complex chips with Electronic Design Automation tools.
June 25, 2025 | 10:00am-11:30am PT
Complex semiconductor chips power today’s cell phones, cars, computers, and more. This on-line Master Class will provide non-technical people who work in and around the chip design industry a high-level
Are you ready to disrupt decades of outdated processes and lead a smarter, more sustainable future in semiconductor manufacturing? While the digital twin has long been a cornerstone of chip design, its power has yet to be fully harnessed on the fab floor. Meanwhile, manufacturers experience increased pressure
June 12, 2025 | 10:00 AM PDT
1 Hour
Artificial intelligence and machine learning (AI/ML) are revolutionizing wireless communications, creating opportunities for innovation and greater efficiency in the communication landscape. However, designing and testing AI/ML algorithms for dynamic and complex wireless environments
Discover how proteanTecs is transforming health and performance monitoring across the semiconductor lifecycle to meet the growing demands of AI and Next-Gen SoCs.
Stop by DAC booth #1616 to experience our latest technologies in action, including interactive live demos and explore our full suite of solutions — designed to boost… Read More
This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows.
Traditional coverage closure methods, relying on constrained-random stimulus generation and iterative manual adjustments, often prove time-consuming and resource-intensive.
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off.
Come learn how the Questa One DFT Verification solution, combined
Wednesday, June 4 – 8:00 AM Pacific
In today’s automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge fault simulation platform designed specifically for complex automotive designs. We’ll
After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More
