Tag: dynamic

Webinar: Introducing Dynamic Simulations in Teaching Using Ansys

Webinar: Introducing Dynamic Simulations in Teaching Using Ansys
by Admin on 12-14-2023 at 3:47 pm

In this webinar, we’ll share implicit and explicit analyses that you can embed in engineering degrees with Ansys LS-Dyna. We’ll illustrate the characteristics of each approach with a particular emphasis on time step definition concepts.

TIME:
JANUARY 30, 2024
11 AM EST / 5 PM CET / 9:30 PM IST

Venue:
Virtual

About this Webinar

Dynamic

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Webinar: Dynamic Thermal Management Using AEDT Icepak

Webinar: Dynamic Thermal Management Using AEDT Icepak
by Admin on 02-06-2023 at 2:08 pm

The ever-increasing need for faster, smaller, and multi-tasking electronic devices poses a significant thermal management challenge for the processor and the system. Manufacturers need to strike a good balance between hardware-based and software-based thermal management strategies to avoid overdesign and minimize the

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CadenceTECHTALK: Static and Dynamic IR Drop Analysis for Thermal Integrity of High-Performance PCB Designs

CadenceTECHTALK: Static and Dynamic IR Drop Analysis for Thermal Integrity of High-Performance PCB Designs
by Admin on 06-01-2022 at 3:00 pm

 

As boards become smaller and faster, the environment for thermal issues becomes increasingly challenging. The thermal management of significant resistive losses in PCB and package structures is critical, especially because these resistive losses are also temperature-dependent, making dynamic and static IR drop

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Recipes for Low Power Verification

Recipes for Low Power Verification
by Bernard Murphy on 03-20-2017 at 7:00 am
Categories: EDA, Synopsys

Synopsys hosted a tutorial on verification for low power design at DVCon this year, including speakers from Samsung, Broadcom, Intel and Synopsys. Verification for low power is a complex and many-faceted topic so this was a very useful update. There is a vast abundance of information in the slides which I can’t hope to summarize… Read More

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Low power physical design in the age of FinFETs

Low power physical design in the age of FinFETs
by Beth Martin on 09-30-2016 at 7:00 am
Categories: EDA, FinFET, Siemens EDA

Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More