Thermal Analysis for 3D SoC Integration

Thermal Analysis for 3D SoC Integration
by Daniel Payne on 11-21-2013 at 7:01 pm

The first time that I saw a DRAM in a ceramic package running on a tester I made the mistake of touching my finger to the metal lid, scorching my finger and teaching me a lesson that ICs can run extremely hot. I’ve read a lot the past few years about 3D IC design, and immediately my mind becomes curious about how an engineer would go… Read More


Architecture-level Power Modeling Methodology at Samsung

Architecture-level Power Modeling Methodology at Samsung
by Daniel Payne on 10-02-2013 at 10:58 am

At DAC this year there was a presentation from Samsung titled, “Profile-based Architecture Power Modeling Methodology for AP/SoC Product”. I’ve been using Samsung Smart Phones for the past four generations, so was very curious about how they have managed to improve the average battery life from less than… Read More


A Brief History of Docea Power

A Brief History of Docea Power
by Daniel Payne on 08-02-2013 at 2:55 pm



Founders

The founder, Ghislain Kaiser, spent about 10 years at STMicroelectronics, mainly in multimedia groups and for the wireless market. At this time, he was a power expert and tasked with making the chips use less power. The first thing he did was to look at what tools existed on the market. They wanted to use off the shelf tools… Read More