Chiplet integration solutions from Keysight at Chiplet Summit

Chiplet integration solutions from Keysight at Chiplet Summit
by Don Dingee on 01-15-2025 at 10:00 am

signal integrity of electrical layer in UCIe

Chiplets continue gaining momentum, fueled in large part by applications for AI and 5G/6G RFICs. Keysight has a strong presence at this year’s Chiplet Summit in Santa Clara, which includes Simon Rance in a super panel discussing “Chiplets: The Key to Solving the AI Energy Gap” and Nilesh Kamdar with a keynote… Read More


Die-to-Die IP enabling the path to the future of Chiplets Ecosystem

Die-to-Die IP enabling the path to the future of Chiplets Ecosystem
by Kalar Rajendiran on 05-30-2022 at 6:00 am

Die to Die Interface Figure of Merit

The topic of chiplets is getting a lot of attention these days. The chiplet movement has picked up more momentum since Moore’s law started slowing down as process technology approached 5nm. With the development cost of a monolithic SoC crossing the $500M and wafer yields of large die-based chips dropping steeply, the decision … Read More


Features of Short-Reach Interface IP Design

Features of Short-Reach Interface IP Design
by Tom Dillinger on 03-08-2021 at 6:00 am

eye diagram

The emergence of advanced packaging technologies has led to the introduction of new types of data communication interfaces.  There are a number of topologies that are defined by the IEEE 802.3 standard, as well as the Optical Internetworking Common Electrical I/O CEI standard. [1,2]  (Many of the configurations of interest … Read More