Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

Webinar: Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Admin on 09-14-2022 at 1:57 pm

Synopsys Webinar | Tuesday, September 20, 2022 | 10 a.m. Pacific

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit

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CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis

CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis
by Admin on 08-29-2022 at 3:22 pm

Date: Tuesday, September 20, 2022

Time: 10:00 – 11:00 (CEST)

Electromigration (EM) impacts design reliability, causing failures over time. That is why it’s important to analyze both the power mesh and signal wires to check that the average, rms, or peak currents will not lead to a permanent failure. Learn how the Cadence

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CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs

CadenceTECHTALK: Taming the Challenges of Advanced Node Digital Designs
by Admin on 11-01-2021 at 2:55 pm

Taming the Challenges of Advanced Node Digital Designs

November 10, 2021

Overview

Although new challenges arise with each node, the move from bulk technologies to advanced node technologies marks a distinctive shift in complexity. Some of the important factors to consider are new devices, challenging and competing design

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Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers

Free Webinar: Silvaco 3D Solver Based Extraction for Device and Circuit Designers
by Tom Simon on 03-20-2018 at 12:00 pm

Designers spend a lot of time looking at their layouts in 2D. This is done naturally because viewing in 2D is faster and simpler than in 3D. It helps that humans are good at extrapolating from 2D to 3D. Analysis software, such as extraction software also spend a lot of time looking at layouts in 2D. While this is fine for approximate results,… Read More


TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More