Optimizing Return from your IP Portfolio

Optimizing Return from your IP Portfolio
by Bernard Murphy on 12-07-2017 at 7:00 am

Given that SoC design today is predicated on IP reuse, you would assume that processes to deliver, maintain and communicate status on reusable IP should be highly optimized. But that’s not necessarily the case, especially when so many design companies have consolidated, each brings its own IP libraries, design flows, license… Read More


Power Exploration at RTL Design with Mentor PowerPro

Power Exploration at RTL Design with Mentor PowerPro
by Bernard Murphy on 09-29-2016 at 7:00 am

There was a comment recently that design for low power is not an event, it’s a process; that comment is Image Removedabsolutely correct. Power is affected by everything in the electronic ecosystem, from application software all the way down to layout and process choices. Yet power as a metric is much more challenging to model and… Read More


Smart Collaborative Design Reduces Business Risk

Smart Collaborative Design Reduces Business Risk
by Pawan Fangaria on 09-10-2014 at 4:00 pm

The semiconductor design industry is ever challenged with increasing chip density, manufacturing complexity with cutting-edge technologies, accommodating multiple IPs with different functionalities from various sources, optimizing power, performance and cost, maximizing manufacturability and reliability and still… Read More