Improve Precision of Parasitic Extraction for Digital Designs

Improve Precision of Parasitic Extraction for Digital Designs
by Admin on 07-15-2025 at 10:00 am

fig1 pex process

By Mark Tawfik

Parasitic extraction is essential in integrated circuit (IC) design, as it identifies unintended resistances, capacitances, and inductances that can impact circuit performance. These parasitic elements arise from the layout and interconnects of the circuit and can affect signal integrity, power consumption,… Read More


Your Symmetric Layouts show Mismatches in SPICE Simulations. What’s going on?

Your Symmetric Layouts show Mismatches in SPICE Simulations. What’s going on?
by Maxim Ershov on 11-07-2022 at 6:00 am

Figure1 6

This Diakopto paper discusses for the first time, a new effect – a false electrical mismatch in post-layout simulations for perfectly symmetric nets. This effect is caused by the difference in distributions of parasitic coupling capacitors over the nodes of parasitic resistor networks, even for symmetric nets. This, in turn,… Read More