Deeper RISC-V pipeline plows through vector-scalar loops

Deeper RISC-V pipeline plows through vector-scalar loops
by Don Dingee on 09-14-2023 at 10:00 am

Atrevido 423 + V16 Vector Unit with its deeper RISC-V pipeline technology, Gazillion

Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled. A while back, Semidynamics… Read More


Configurable RISC-V core sidesteps cache misses with 128 fetches

Configurable RISC-V core sidesteps cache misses with 128 fetches
by Don Dingee on 04-25-2023 at 6:00 am

Gazzillion misses 2

Modern CPU performance hinges on keeping a processor’s pipeline fed so it executes operations on every tick of the clock, typically using abundant multi-level caching. However, a crop of cache-busting applications is looming, like AI and high-performance computing (HPC) applications running on big data sets. SemidynamicsRead More


How to prevent execution surprises for Cortex-M7 MCU?

How to prevent execution surprises for Cortex-M7 MCU?
by Eric Esteve on 08-06-2015 at 11:00 am

ARM Cortex-A series processor core (A57, A53) are well known in the high performance market segments, like Application Processor for smartphone, Set-Top-Box or networking. If you look at the electronic market you realize that multiple applications are cost sensitive and doesn’t need such high performance processor core. … Read More