New CoreLink IP ties in mobile GPU coherently

New CoreLink IP ties in mobile GPU coherently
by Don Dingee on 10-29-2015 at 7:00 am

A mobile GPU is an expensive piece of SoC real estate in terms of footprint and power consumption, but critical to meeting user experience demands. GPU IP tuned for OpenGL ES is now a staple in high performance mobile devices, rendering polygons with shading and texture compression at impressive speeds.

Creative minds in the desktop… Read More


Why Modern SoC need cache-coherent NoC?

Why Modern SoC need cache-coherent NoC?
by Eric Esteve on 08-03-2015 at 4:00 pm

Launching high technology product on the semiconductor market after your competitors is not necessarily a weakness. NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. Created about 20 years… Read More


Learning Cache Coherency and Cache Coherent Interconnects: ARM White Paper

Learning Cache Coherency and Cache Coherent Interconnects: ARM White Paper
by Eric Esteve on 08-19-2014 at 11:08 am

Cache Coherency is the type of concept that you think you understand, until you try to explain it. It could be wise to come back to fundamentals, and ask what does coherency means to an expert. I have surf the web, found several white papers on ARM site, and now I can try to share these fresh lessons learned (or you may prefer to download… Read More


Taming The Interconnect In Real World For SoCs

Taming The Interconnect In Real World For SoCs
by Pawan Fangaria on 12-13-2013 at 1:30 pm

Interconnect plays a significant role in the semiconductor design of a SoC; if not architected and handled well, it can lead to an overdesigned SoC impacting on its power, performance and area. Since a SoC generally contains multiple IPs requiring different data paths to satisfy varying latency and performance cycles, it has … Read More


MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000

MUST: DSP ready solution for tomorrow smartphone based on CEVA-XC 4000
by Eric Esteve on 02-24-2013 at 5:13 am

Like Guiness dark beer, competition is good for you! I mean good for end user, as it pushes DSP IP supplier to provide ever better solution. I am not talking about me-to type of competition, like that we have seen in the past with IBM trying to displace TI at Nokia, by offering a LEAD (DSP IP core from TI used in every NOKIA wireless phone… Read More


Cadence sets the Global Standards in VIP for AMBA based SoC

Cadence sets the Global Standards in VIP for AMBA based SoC
by Eric Esteve on 11-12-2012 at 11:48 am

We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More