White Paper – Mixed Signal Verification for Nanometer SOCs

White Paper – Mixed Signal Verification for Nanometer SOCs
by Tom Simon on 08-19-2020 at 10:00 am

Mixed signal SOCs

The number of touchpoints between analog and digital circuits in high performance SoCs is increasing. This is not a problem because it is possible to implement critical analog blocks directly on nanometer scale digital ICs. However, in many cases digital interfaces or digital feedback circuitry configures these analog blocks… Read More


Patterns looking inside, not just between, logic cells

Patterns looking inside, not just between, logic cells
by Don Dingee on 12-27-2013 at 5:00 pm

Traditional logic testing relies on blasting pattern after pattern at the inputs, trying to exercise combinations to shake faults out of logic and hopefully have them manifested at an observable pin, be it a test point or a final output stage. It’s a remarkably inefficient process with a lot of randomness and luck involved.

Getting… Read More