Can RISC-V Help Recast the DPU Race?

Can RISC-V Help Recast the DPU Race?
by Jonah McLeod on 08-26-2025 at 10:00 am

Can RISC V Help Qualcomm

ARM’s Quiet Coup in DPUs

The datacenter is usually framed as a contest between CPUs (x86, ARM, RISC-V) and GPUs (NVIDIA, AMD, custom ASICs). But beneath those high-profile battles, another silent revolution has played out: ARM quietly displaced Intel and AMD in the Data Processing Unit (DPU) market.

DPUs — also called SmartNICs… Read More


Intel’s Pearl Harbor Moment

Intel’s Pearl Harbor Moment
by Daniel Nenni on 08-25-2025 at 10:00 am

Pearl Harbor Memorial Hawaii

There is a lot of talk about where Intel went wrong, the latest is missing AI, but people seem to forget one of the more defining blunders in the history of Intel. In April of 2012 Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Mark Bohr, a 33+ year Intel fellow, and Brad Heaney, the Ivy Bridge… Read More


Software-defined Systems at #62DAC

Software-defined Systems at #62DAC
by Daniel Payne on 08-06-2025 at 10:00 am

siemens panel on software-defined systems min

Modern EVs are prime examples of software-defined systems, so I attended a #62DAC panel session hosted by Siemens to learn more from experts at Collins Aerospace, Arm, AMD and Siemens. Here’s the list of panelists that span several domains, and what follows is my paraphrase of the discussion topics.

Panel Discussion

Q: How does… Read More


Enabling the AI Revolution: Insights from AMD’s DAC Keynote

Enabling the AI Revolution: Insights from AMD’s DAC Keynote
by Admin on 08-01-2025 at 1:00 pm

Screenshot 2025 08 27 160739

In a keynote by Michaela Blott, AMD Senior Fellow,  at the 62nd Design Automation Conference (DAC) on July 8, 2025, explored the trends shaping the AI revolution, emphasizing inference efficiency and hardware customization. While acknowledging AMD’s efforts in scaling GPUs and achieving energy efficiency goals (30x… Read More


Essential Debugging Techniques Workshop

Essential Debugging Techniques Workshop
by Admin on 06-12-2025 at 1:48 pm

Essential Debugging Techniques Workshop

This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado

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Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques

Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques
by Admin on 06-12-2025 at 1:45 pm

Description

Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx… Read More


Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration
by Admin on 06-12-2025 at 1:40 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications… Read More


Achieving Timing Closure in FPGA Designs Workshop

Achieving Timing Closure in FPGA Designs Workshop
by Admin on 06-12-2025 at 1:37 pm

Achieving Timing Closure in FPGA Designs Workshop

Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.

Gain hands-on experience … Read More


Webinar: Getting Started with the Vitis Unified IDE

Webinar: Getting Started with the Vitis Unified IDE
by Admin on 06-12-2025 at 1:33 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process… Read More


Webinar: Maximizing RFSoC Potential with Functionality and Configurability

Webinar: Maximizing RFSoC Potential with Functionality and Configurability
by Admin on 06-12-2025 at 1:28 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With the RFSoC, configuring data converters is crucial for advanced system development, but the complexity often overwhelms… Read More