At advanced nodes, observed defectivity, variability, and process-window behavior increasingly extend beyond what EPE and CD metrics can characterize. Closing that gap requires new ways to model, optimize, and measure patterning as well
Ever since the Silicon Catalyst 2023 Semiconductor Industry Forum (“Welcome to our AI Wonderland”) I’ve been convinced that the Nobel Prize committee needs to consider awarding a posthumous award to Sir Arthur.
To remind you, Sir Arthur’s “2001: A Space Odyssey” movie was released in 1968. At that point in time… Read More
TSMC is describing an artificial intelligence boom that reaches beyond accelerator chips into the wider computing infrastructure needed to support increasingly capable AI systems. On the recent investor call, Chairman and CEO Dr. C.C. Wei presents strong demand, persistent supply constraints and an ambitious expansion … Read More
Designing high-performance multi-chiplet semiconductor packages for hyperscale, HPC and AI applications combines cutting-edge innovation with practical optimization. Embedded silicon bridge substrates enable cost-effective solutions by using base substrates such as organic laminates or redistribution-layer (RDL)… Read More
Agentic AI is transforming computing systems into intelligent platforms capable of reasoning, planning, orchestrating tools, and acting autonomously. These new AI workloads… Read More
Sheraton Grand at Wild Horse Pass
Phoenix, Arizona
March 1-4, 2027
The 23rd Annual IMAPS Device Packaging Conference (DPC 2027) will be held in Phoenix, Arizona, on March 1-4, 2027. It is an international event organized by the International… Read More
The rapid growth of AI at the edge is forcing SoC architects to rethink traditional processor designs. Dedicated NPUs deliver impressive performance for today’s models, but evolving AI workloads, increasing system complexity and growing pressure on power and silicon budgets are exposing the limitations of fixed-function… Read More
At DAC 2026 I had the opportunity to speak with Juan Rey, CTO Siemens EDA about the Calibre product used for IC physical verification, circuit verification, 3D IC and DFM optimization. Juan has been involved with Calibre since 2001, served on the Board of Directors of Silicon Integration Initiative (SI2), on the Executive Technology… Read More
