Enabling Agentic AI: Memory, Interconnect and Security Solutions for Autonomous Intelligence
October 22, 2026 8:00 am – 1:30 pm PDT
About Event
Agentic AI is transforming computing systems into intelligent platforms capable of reasoning, planning, orchestrating tools, and acting autonomously. These new AI workloads… Read More
ADVANCED PACKAGING FOR SCALABLE AI: CONNECTING COMPUTE, MEMORY, POWER AND PHOTONICS
Sheraton Grand at Wild Horse Pass
Phoenix, Arizona
March 1-4, 2027
The 23rd Annual IMAPS Device Packaging Conference (DPC 2027) will be held in Phoenix, Arizona, on March 1-4, 2027. It is an international event organized by the International… Read More
The rapid growth of AI at the edge is forcing SoC architects to rethink traditional processor designs. Dedicated NPUs deliver impressive performance for today’s models, but evolving AI workloads, increasing system complexity and growing pressure on power and silicon budgets are exposing the limitations of fixed-function… Read More
At DAC 2026 I had the opportunity to speak with Juan Rey, CTO Siemens EDA about the Calibre product used for IC physical verification, circuit verification, 3D IC and DFM optimization. Juan has been involved with Calibre since 2001, served on the Board of Directors of Silicon Integration Initiative (SI2), on the Executive Technology… Read More
TSMC is introducing an AI Design Kit, or ADK, to help artificial intelligence tools make better use of its semiconductor manufacturing knowledge. The idea is to give AI agents that run chip-design workflows a technology-specific foundation, so they can adjust designs toward performance, power and area targets with less manual… Read More
Synopsys today announced its AgentEngineerTM solutions portfolio and AutopilotTM Platform, advancing a fundamental paradigm shift in electronic design automation (EDA): moving beyond AI copilots toward autonomous engineering agents. Following a recent technical briefing with Thomas Andersen, Vice President of AI and… Read More
👉 This is Part 2 of an editorial series on the evolving economics of AI inference. If you missed Part 1, where I broke down the shift toward full-system integration, the lessons from the AI Infra Summit, and the “no forks” open-source philosophy, you can read it HERE: Beyond the Accelerator: Why Silicon Challengers … Read More
Running AI models efficiently at the edge is about more than hardware TOPS. In this session, we’ll walk through the end-to-end process of porting, analysing and optimising modern AI models for edge GPUs, using Qwen 3.5 as a practical example. Learn how to take a model from framework to deployment, identify performance bottlenecks,… Read More
Featured Speaker:
- Kant Deshpande, Architect, Technical Product Management, Synopsys
As AI/ML clusters scale toward 800G, 1.6T, and beyond, the optical DSP/retimer functions inside conventional transceivers (FRO) are becoming a significant bottleneck — adding power, latency, and cost to every link at a time when interconnects… Read More
