At a DAC Accellera panel this year there was some discussion on cross-company collaboration in training. The theory is that more collaboration would mean a larger training set and therefore higher accuracy in GenAI (for example in RTL generation). But semiconductor companies are very protective of their data and reports of copyrighted… Read More
Webinar: How PCIe Multistream Architecture is enabling AI Connectivity at 64 GT/s and 128 GT/s
Featured Speakers:
- Diwakar Kumaraswamy, Sr. Staff Technical Product Manager, Synopsys
AI and HPC workloads push fabric speeds to deliver higher parallelism and utilization at extreme data rates. To support these higher rates, the controller architecture needs to be completely redefined resulting in the new PCIe controller
