Daniel is joined by Nagesh Gupta, CEO of llmda.ai. Nagesh has built a career spanning multiple aspects of system design and development at companies including Hewlett-Packard, Cadence, Xilinx, and Lattice Semiconductor. He is also a serial entrepreneur. Nagesh founded Taray, Inc., which developed memory interface generators… Read More
The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens,… Read More
Agentic AI is often presented as a revolutionary shift in semiconductor manufacturing, driven by large language models and generative AI. However, this framing overlooks an important reality: today’s advances are built on decades of prior work. As Jonathan Holt of PDF Solutions emphasizes in his recent keynote at the APCM 2026… Read More
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Embedded systems programs rarely fail because any one team lacks capability. They fail because critical engineering artifacts drift out of alignment over time and distance.
This includes requirements, architecture, implementation, verification, hardware bring-up, firmware,… Read More
“How Will Agentic AI Change Chip Design and Verification?” features EDA and emerging agentic AI company executives and entrepreneurs discussing changes within chip design and verification as agentic AI tools become more mainstream. Panelists will distill the excitement surrounding the innovation in chip design and verification,… Read More
Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More
In a break from our academic-centric picks, here we look at an agentic verification flow developed within a semiconductor company. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More
NetApp recently hosted a webinar on Agentic AI as the future for EDA and implications for infrastructure. Good list of panelists including Mahesh Turaga (VP Cadence Cloud) with an intro preso on infrastructure and agentic AI at Cadence, then our own Dan Nenni (Mr. SemiWiki) moderating, Khaled Heloue (Fellow AMD, CAD CAD/Methodology/AI),… Read More
Custom IC design has demanding technical requirements to produce accurate simulation results for timing and power analysis in the shortest run times. EDA vendors have been rushing to use AI and ML technology to meet these analysis requirements. I attended a webinar from Siemens on accelerating iterative design cycles with Solido… Read More
