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Embedded systems programs rarely fail because any one team lacks capability. They fail because critical engineering artifacts drift out of alignment over time and distance.
This includes requirements, architecture, implementation, verification, hardware bring-up, firmware,… Read More
“How Will Agentic AI Change Chip Design and Verification?” features EDA and emerging agentic AI company executives and entrepreneurs discussing changes within chip design and verification as agentic AI tools become more mainstream. Panelists will distill the excitement surrounding the innovation in chip design and verification,… Read More
Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More
In a break from our academic-centric picks, here we look at an agentic verification flow developed within a semiconductor company. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More
NetApp recently hosted a webinar on Agentic AI as the future for EDA and implications for infrastructure. Good list of panelists including Mahesh Turaga (VP Cadence Cloud) with an intro preso on infrastructure and agentic AI at Cadence, then our own Dan Nenni (Mr. SemiWiki) moderating, Khaled Heloue (Fellow AMD, CAD CAD/Methodology/AI),… Read More
Custom IC design has demanding technical requirements to produce accurate simulation results for timing and power analysis in the shortest run times. EDA vendors have been rushing to use AI and ML technology to meet these analysis requirements. I attended a webinar from Siemens on accelerating iterative design cycles with Solido… Read More
I have seen a lot of EDA tool demos in my time. More than I want to admit. The perceived quality of the demo usually came down to a combination of the speed of the tool, quality of results and the ease of navigating through the graphical user interface. For the last item, how easy the interface was on the eyes, how clear were the relationships… Read More
For decades, chip design has been a delicate balance of creativity and drudgery. Architects craft detailed specifications, engineers read those documents line by line, and teams write and debug thousands of lines of Verilog and UVM code. Verification alone can consume up to 35 percent of a project’s cost and add many months to … Read More
In the business press today I still find a preference for reporting proof-of-concept accomplishments for AI applications: passing a bar exam with a top grade, finding cancerous tissue in X-rays more accurately than junior radiologists, and so on. Back in the day we knew that a proof-of-concept, however appealing, had to be followed… Read More
