3D-IC Physical Design

3D-IC Physical Design
by Pawan Fangaria on 02-22-2012 at 10:00 am

When process nodes reached 28 nm and below, it appeared that design density is reaching a saturation point, hitting the limits of Moore’s law. I was of the opinion that the future of microelectronic physical design was limited to 20 and 14 nm being addressed by technological advances such as FinFETs, double patterning, HKMG (High-k… Read More