Semiconductor Device Physics, Lab in a Box

Semiconductor Device Physics, Lab in a Box
by Daniel Payne on 09-13-2017 at 12:00 pm

One of my favorite classes in college was the lab exercise, mostly because we actually got to use real electronics and then measure something, finally writing it up in our lab notebooks. The issue today is that a college student taking Electrical Engineering probably doesn’t have much access to 10nm FinFET silicon for use… Read More


IO Design Optimization Flow for Reliability in 28nm

IO Design Optimization Flow for Reliability in 28nm
by Daniel Payne on 07-31-2014 at 5:00 pm

User group meetings are a rich source of information for IC designers because they have actual designers talking about how they used EDA tools in their methodology to achieve a goal. Engineers at STMicroelectronicspresented at a MunEDAUser Group on the topic: I/O Design Optimization Flow For Reliability In Advanced CMOS Nodes.… Read More