2025 Outlook with Larry Zu of Sarcina Technology

Tell us a little bit about yourself and your company. 

I’m Larry Zu, Founder and CEO of Sarcina Technology. I’ve grown Sarcina from just designing packages for a few small companies to handling the entire post-silicon ecosystem, including package design, assembly, testing, qualification and production services for the top semiconductor companies in the world. I began my career at Bell Labs, before moving to DEC, Intel, and TSMC.  Along the way, I acquired deep skills on how to develop successful products including the Alpha, Itanium 2, Pentium 4, and XBOX 360 microprocessors.

Over my career, I have taped out nearly 1,000 packages with a greater than 99% first tape-out success rate. I’ve applied those skills to build Sarcina, a company that works with the world’s top foundries to ensure high quality products. We manage from the simplest to the most complex of packages. Companies forward their wafers from their foundries and Sarcina does the rest.  Wafers in, packaged chips out.

What was the most exciting high point of 2024 for your company? 

There were many great successes in 2024, so this is a difficult question. If I had to pick one, perhaps I would cite our work on Bump Pitch Transformers (BPT). I know it’s an odd name, but what this work does is reduce the cost and complexity of 2.5D package designs.

Current advanced 2.5D packaging uses a substrate to transpose a chip’s microbump pitch from 40-50 micrometers to the package’s 130 micrometer bump pitch. This is typically done with a silicon TSV (through-silicon via) interposer. These substrates are very expensive, in short supply, and complex to design, resulting in lead-time and cost challenges for many advanced designs.

Our BPT approach uses RDL interconnect or silicon bridge technologies, replacing silicon TSV interposers with more cost-effective re-distribution layers (RDL). This architecture is ideal for homogeneous and heterogeneous chiplet integration, targeting high-performance computing (HPC) devices for AI, data center, microprocessor, and networking applications.

What was the biggest challenge your company faced in 2024? 

Our biggest challenge is actually not a technical one. Sarcina’s strength and fundamental differentiation is our ability to complete high-performance engineering projects. Over the past 12 years, Sarcina has taped out more than 100 packages, all first-time successes. We’ve never re-taped out a single package.

The challenge is to get the word out to more companies who can benefit from our capabilities. We can help small to mid-sized ASIC companies and large system houses be more successful.

How is your company’s work addressing this biggest challenge?  

I personally do a lot of presentations at many trade shows and industry events to help spread the word about Sarcina’s Application Specific Advanced Package (ASAP) Service. Our work here on SemiWiki is also a key part of that strategy.

What do you think the biggest growth area for 2025 will be, and why?

Advanced packaging is now setting the trend for the next level of innovation. The know-how to integrate multiple devices in an advanced package provides the margin of victory. Sarcina is at the forefront, enabling these trends.

There will be growth in many areas as a result. Some markets we are currently enabling include AI, networking, data center, high-speed comms, and medical.

How is your company’s work addressing this growth? 

We continue to build more advanced flows that embody our substantial experience. Our partnerships also help to expand our reach and impact. The work we are doing with Keysight is an example of this. So is the work we are doing with Intel Foundry Services (IFS) Accelerator Design Services Alliance.

What conferences did you attend in 2024 and how was the traffic?

We attended quite a few events in 2024:

• Chiplet Summit
• OFC (Optical Fiber Communications)
• IEEE MTT-S International Microwave Symposium
• Silicon Catalyst Spring Portfolio Conference
• Design Automation Conference (DAC) (I was a speaker at the Keysight Theater)
• IEEE Electronics System-Integration Technology Conference (ESTC)
• Silicon Catalyst Semiconductor Industry Forum

All these conferences are packed with people because they address hot topics in high performance computing and communication for AI applications inside a semiconductor ASIC chip. As semiconductor packaging becomes more and more important to build advanced ASIC chips, we observe more traffic to our booth during these conferences.

Will you attend conferences in 2025? Same or more?

We plan to attend similar shows in 2025, with some possible additions.  You can visit https://sarcinatech.com/upcoming-events/ to see the latest plans we have for show attendance.

How do customers engage with your company?

You can certainly stop by and visit us at the shows we will attend. You can also reach out to us on our website here: https://sarcinatech.com/contact/. We’ll respond quickly and work with you to define how we can make you more successful.

Additional questions or final comments? 

Semiconductor technology is evolving rapidly. Monolithic integration is being replaced by complex multi-chip system in package design.  These designs represent substantial challenges with many new effects to be modeled and tamed. Sarcina has the experience, skills and track record to help you overcome these challenges. Give us a call and find your margin of victory.

Also Read:

Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers

How Sarcina Revolutionizes Advanced Packaging #61DAC

Sarcina Teams with Keysight to Deliver Advanced Packages