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CEO Interview: Dr. J Provine of Aligned Carbon

CEO Interview: Dr. J Provine of Aligned Carbon
by Daniel Nenni on 11-17-2023 at 6:00 am

Cyclotron Road Cohort Five

J Provine, PhD, is the CEO and co-founder of Aligned Carbon, a startup that has developed a breakthrough synthesis and purification technology for aligned, semiconducting carbon nanotubes (CNTs) at wafer scale. His team believes that Aligned Carbon is the crucial missing piece in an industry that has long been hopeful of –… Read More


RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation

RISC-V Summit Buzz – Ron Black Unveils Codasip’s Paradigm Shift for Secured Innovation
by Mike Gianfagna on 11-16-2023 at 10:00 am

Ron Black

Codasip is a processor solutions company with an expanding footprint. It is Europe’s leading RISC-V organization with a global presence. Codasip reports billions of chips already use its technology.  You can learn more about Codasip here, The company has made some announcements recently that expand its offerings in terms … Read More


NoCs give architects flexibility in system-in RISC-V design

NoCs give architects flexibility in system-in RISC-V design
by Don Dingee on 11-16-2023 at 6:00 am

Power domains and crossings into NoC for system in RISC V design

RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem. Those are all necessary steps to obtaining system-level performance. But is that attention sufficient? Architects who have ventured into larger system-on-chip (SoC) … Read More


The Coming China Chipocalypse – Trade Sanctions Backfire – Chips versus Equipment

The Coming China Chipocalypse – Trade Sanctions Backfire – Chips versus Equipment
by Robert Maire on 11-15-2023 at 10:00 am

China Sino US
  • China Chip Sanctions have had opposite of intended effect
  • Helps AMAT, LRCX, KLAC & TEL- Hurts Micron and GloFo
  • Tsunami of Chinese capacity will hurt memory & 2nd tier chip makers
  • The probability of a much longer chip downcycle is increasing
China is cornering the market on Semiconductor equipment

Quarterly reports from… Read More


Accelerating Development for Audio and Vision AI Pipelines

Accelerating Development for Audio and Vision AI Pipelines
by Bernard Murphy on 11-15-2023 at 6:00 am

AI pipeline min

I wrote previously that the debate over which CPU rules the world (Arm versus RISC-V) somewhat misses the forest for the trees in modern systems. This is nowhere more obvious that in intelligent audio and vision: smart doorbells, speakers, voice activated remotes, intelligent earbuds, automotive collision avoidance, self-parking,… Read More


Generative AI for Silicon Design – Article 3 (Simulate My Design)

Generative AI for Silicon Design – Article 3 (Simulate My Design)
by Anshul Jain on 11-14-2023 at 10:00 am

Generative AI for Silicon Design

Generative AI has time and again showcased its power to understand, predict, and explain a myriad of phenomena. Beyond its famed applications in art and text, it’s making ripples in the niche realm of hardware engineering. In this article, our exploration focuses on the potential of Generative AI to comprehend and predict… Read More


Uniquely Understanding Challenges of Chip Design and Verification

Uniquely Understanding Challenges of Chip Design and Verification
by Daniel Nenni on 11-14-2023 at 6:00 am

Jean Marie Brunet (1)

Jean-Marie Brunet is Vice President and General Manager of Siemens Hardware-Assisted Verification. He and I spoke recently about how different his hardware group is from the rest of the software-centric EDA product space and why a hardware-oriented EDA vendor like Siemens fully understands the challenges of the chip design… Read More


New STA Features from Cadence

New STA Features from Cadence
by Daniel Payne on 11-13-2023 at 10:00 am

Tempus DRA Suite

Static Timing Analysis (STA) has been an EDA tool category for many years now, yet with each new generation of smaller foundry process nodes come new physical effects that impact timing, requiring new analysis features to be added. For advanced process nodes, there are five different types of analysis that must be included when… Read More


Successful 3DIC design requires an integrated approach

Successful 3DIC design requires an integrated approach
by Kalar Rajendiran on 11-13-2023 at 6:00 am

Siemens EDA 3DIC Graphics

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More


Podcast EP193: A Look at the Engineering Tracks for DAC 2024 with Frank Schirrmeister

Podcast EP193: A Look at the Engineering Tracks for DAC 2024 with Frank Schirrmeister
by Daniel Nenni on 11-10-2023 at 10:00 am

Dan is joined by Frank Schirrmeister. Frank is vice president of solutions and business development at Arteris. He leads activities for industry verticals, including automotive and enterprise computing and technology horizontals like artificial intelligence, machine learning, and safety. For DAC 2024, Frank is the vice… Read More