- Understanding the expected functionality of designs.
- Developing testing and regression plans.
- Designing and developing verification environment.
- Running RTL and gate-level simulations/regression.
- Code/functional coverage development, analysis and closure.
- Work experience and rank are not limited.
- Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…).
- Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
- Self motivated, good communication skill and team work spirit.
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To view the job application please visit www.verisilicon.com.