Ansys IDEAS Digital Forum Banner 1

Verification Field Application Engineer – Simulation

Verification Field Application Engineer – Simulation
by Admin on 09-04-2020 at 7:24 am

Website Cadence

At this time, Cadence is not providing work authorization sponsorship for this position.

As a Principal Application Engineer in Cadence’s Advanced Verification Solutions Division you will be responsible for solving customer verification challenges with leading edge technologies and methodologies. Your main focus will be on Cadence’s Xcelium verification platform. You will support customers in deploying Xcelium Single-Core and Multi-Core, vManager and Perspec solutions on environments with a mix of SystemVerilog, SystemC/C/C++, Verilog & VHDL using industry standard verification methodologies such as UVM. You will also be responsible for support of related low power, HDL and HVL debug, acceleration, linting and formal solutions.

Location; Los Angeles, CA (preferred) or Orange County, CA

Key responsibilities in this position are to:

• Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support

• Provide in-depth technical assistance in collaboration with R&D to help support verification flows to secure design wins

• Understand the competitive landscape and continuously work on differentiating Cadence’s solutions.

• Write technical product literature such as application notes and technical articles.

The major focus of this role will be on RTL and Gate-Level simulation and will require strong knowledge and experience in the following areas:

• Verification knowledge such as SystemVerilog HVL and UVM testbench architecture, development and debug

Minimum Required Experience:

·   At this time, Cadence is not providing work authorization sponsorship for this position.

·      BS, MS or PhD in Electronic Engineering

·      Strong software, HDL design and verification skills

·      Detailed understanding of SystemVerilog and UVM

·      Ability to quickly analyze verification environments and design complexity

·      Strong verbal and written communication skills

·      Ability to interact effectively with both external customers and R&D teams

Additional Desired Experience:

·      Experience with SystemC

·      Experience with VHDL, Verilog, C/C++

·      Experience with coverage closure, low power simulations

·      Ability to write scripts (Perl, Python or Ruby, TCL)

Apply for job

To view the job application please visit